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McKenney" , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, kernel-team@meta.com, parri.andrea@gmail.com, boqun.feng@gmail.com, j.alglave@ucl.ac.uk, luc.maranget@inria.fr, Joel Fernandes References: <72c804c8-2511-4349-a823-bc1de8bb729e@rowland.harvard.edu> <2f20e7cf-7c67-4ad3-8a0c-3c1d01257ae4@rowland.harvard.edu> From: Jonas Oberhauser In-Reply-To: <2f20e7cf-7c67-4ad3-8a0c-3c1d01257ae4@rowland.harvard.edu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CM-TRANSID:GxC2BwC38SUMcExm4emUCA--.12318S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZFyDJw1fWr4xKr15KryfWFg_yoW5CrWfpa 13Ka4UKr4DJw4vk3Wq9FsIqFyF9a1rJrWUXr93twsakas0gr1IgF15t3yUuF9rXrZ7Z3Wj vr13tas7ua4DArJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkK14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcVAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kI c2xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14 v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkG c2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6rW3Jr0E3s1lIxAIcVC2z280aVAFwI0_Jr0_ Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbU UUUUU== X-CM-SenderInfo: 5mrqt2oorev25kdx2v3u6k3tpzhluzxrxghudrp/ Am 5/18/2024 um 2:31 AM schrieb Alan Stern: > On Thu, May 16, 2024 at 10:44:05AM +0200, Hernan Ponce de Leon wrote: >> On 5/16/2024 10:31 AM, Jonas Oberhauser wrote: >>> >>> >>> Am 5/16/2024 um 3:43 AM schrieb Alan Stern: >>>> Hernan and Jonas: >>>> >>>> Can you explain more fully the changes you want to make to herd7 and/or >>>> the LKMM?  The goal is to make the memory barriers currently implicit in >>>> RMW operations explicit, but I couldn't understand how you propose to do >>>> this. >>>> >>>> Are you going to change herd7 somehow, and if so, how?  It seems like >>>> you should want to provide sufficient information so that the .bell >>>> and .cat files can implement the appropriate memory barriers associated >>>> with each RMW operation.  What additional information is needed?  And >>>> how (explained in English, not by quoting source code) will the .bell >>>> and .cat files make use of this information? >>>> >>>> Alan >>> >>> >>> I don't know whether herd7 needs to be changed. Probably, herd7 does the >>> following: >>> - if a tag called Mb appears on an rmw instruction (by instruction I >>> mean things like xchg(), atomic_inc_return_relaxed()), replace it with >>> one of those things: >>>   * full mb ; once (the rmw) ; full mb, if a value returning >>> (successful) rmw >>>   * once (the rmw)   otherwise >>> - everything else gets translated 1:1 into some internal representation >> >> This is my understanding from reading the source code of CSem.ml in herd7's >> repo. >> >> Also, this is exactly what dartagnan is currently doing. >> >>> >>> What I'm proposing is: >>> 1. remove this transpilation step, >>> 2. and instead allow the Mb tag to actually appear on RMW instructions >>> 3. change the cat file to explicitly define the behavior of the Mb tag >>> on RMW instructions >> >> These are the exact 3 things I changed in dartagnan for testing what Jonas >> proposed. >> >> I am not sure if further changes are needed for herd7. > > Okay, good. This answers the first part of what I asked. What about > the second part? That is, how will the changes to the .def, .bell, and > .cat files achieve your goals? > > Alan Firstly, we'd allow 'mb as a barrier mode in events, e.g. instructions RMW[{'once,'acquire,'release,'mb}] then the Mb tags would appear in the graph. And then I'd define the ordering explicitly. One way is to say that an Mb tag orders all memory accesses before(or at) the tag with all memory accesses after(or at) the tag, except the accesses of the rmw with each other. This is the same as the full fence before the read, which orders all memory accesses before the read with every access after(or at) the read, plus the full fence after the write, which orders all memory accesses before(or at) the write with all accesses after the write. That would be done by adding [M] ; (po \ rmw) & (po^?; [RMW_MB] ; po^?) ; [M] to ppo. One could also split it into two rules to keep with the "two full fences" analogy. Maybe a good way would be like this: [M] ; po; [RMW_MB & R] ; po^? ; [M] [M] ; po^?; [RMW_MB & W] ; po ; [M] Hope that makes sense, jonas