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Tue, 21 May 2024 04:09:28 -0700 From: Vidya Sagar To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH V2] PCI: Extend ACS configurability Date: Tue, 21 May 2024 16:39:25 +0530 Message-ID: <20240521110925.3876786-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-NVConfidentiality: public Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DD:EE_|IA1PR12MB9030:EE_ X-MS-Office365-Filtering-Correlation-Id: 2af04927-393b-4ef0-5b92-08dc79868225 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|82310400017|1800799015|376005; X-Microsoft-Antispam-Message-Info: =?utf-8?B?RHpxNVA0T0pKaGFSYVNMUmwwOWxaVDNrMnUrbk9mUmdLeEh6aTltY29YQ0Fi?= =?utf-8?B?ZmxvbzRuWWtLSmdxb1lTWE1RNUwyaTErM21OYklWelpkZ1VxQktFbUptWHdI?= =?utf-8?B?NVJ4MHJsQlBwVkFOdUhaUmRIT200eDI5QXhlTTQ3VTdjc1k0RVc5cVZMQWto?= =?utf-8?B?MGpmT1hadnBEMXZJTSt4TXR6U1RXd00zVzJ2S0R4RmIxcnphSDA3bnpSV1h6?= =?utf-8?B?OStvdE42SEluTUlHS0l3MzNkbzExOWFlV29NY21FYnJIVHg0VnovT3ZkWUZH?= =?utf-8?B?MHl3Z0JGdi8vRmJjQnBhdHg4TkxwdFk1TFZiOTcreWxxNUdQS1Jad2k4c1Za?= =?utf-8?B?UGU5K0NaL3IwNURKTDN5VzRINWZ1Vk5Hc2J4VmVaSENTWE1jK1R3U0NucWx0?= =?utf-8?B?RnVwanJyMkltSUwrbkxjNFdLeXZva0R1dTRhZ0hQeHhpTUxhcmw5RS9SMWs4?= =?utf-8?B?WXdyNS9vbTRDU2NxaDI1dk5pY014Zm5zNExGTU9EOTBpd2JUVnp5NURudVlZ?= =?utf-8?B?RStROVZWeVJxM01ONi9FVTRqMWVveVB6djE3RUhpc1JyZndPZ1AvbzRjdzha?= =?utf-8?B?K0dOemZXaUlTWjNobUJaOTRVY0ZadFV4aE05SHdEcUR0TFlBVERwRDhRSHVm?= =?utf-8?B?ai9XMExZc3pOSEd6dWlWWGQ3SFpibWdPLy81T1ZrSks0cXdVME5iZGc2YVh3?= =?utf-8?B?bHh4K2xHbEVqMy95eEhvUWNKaEJ1V2U4RnFmUG5KTlV2LzZJYkQrOFVMSXJI?= =?utf-8?B?L1ZxNUoxZnJmTmthR1RUeUYxbEYxNVhyb09USVBlK2hEMmtXV2pXWEZtQ2N0?= =?utf-8?B?TWFMN2tYNDFhcXJMdi9ZVFVtSU5LM1dML1RPUDNEeURWTTlXc0dWOGJ0bUhQ?= =?utf-8?B?RTFLdXhmeDc4MmhHbEs3S0dyT3dEd0JrTXkra1hpTTgvbnpRS0VMVDl5MEg1?= =?utf-8?B?ZkFhNE9oQ3NpOEtTWmJ3Qm9oQWk1NEFNSkNlR2tPalZFeWpyRk53U29FVldV?= =?utf-8?B?TmN3Wjh0WnVMYnFhaEdUZmwrT3JDWDEyRHMzSHM3bzIyT0NSc1lDdVhXb0Fh?= =?utf-8?B?dGc1RmFQOU9PVXUrZUNEY1JKYVM1aFBTWVNMK1g3N1VuaFkrRWZ2dFlvQ09B?= =?utf-8?B?c1ZCbmgxRDk1WHdiT2pPV0NYQk9FUXI3UC9LU2t5MjExd2JNWHYxNlQwRDJj?= =?utf-8?B?UUdKUERRS3pvT2ZwYnJGOWw4d2RFOXN4cUpYYktxQ085cHdvMFBqOVk0eEp1?= =?utf-8?B?MTA0TGFTRkZoVWtuMlc5L1ptclZ6aUNmU1lBQ1U5NUFNdHhXcGJYbHplemFU?= =?utf-8?B?SU1IRENlS01hQzFDR3cyTTNZeXkvSWNscjdXNXdrVk15dkdWendNa0l2dDhK?= =?utf-8?B?YWVnSEJrWkZsbmF5ZkZUVUd4ZHhaTTN1dWQwN0Jyb0lsMDNhMHZzaVl0dGMx?= =?utf-8?B?SGhxSUxOOG5GZytmVWR6NFBDbktyQk8wd1J6QjAzQTMwWGs3SHlwVUhJOVcz?= =?utf-8?B?QS9USmVJSE10NDg2UTNTci9uUEk1dlRUejZhamtORlIxdTExTkxkTDFaVGti?= =?utf-8?B?STdCSDB4bENmc2RBZU5YRUp3emxYSjY4cTJkWEh6M1JTZTZIZW90Ulp3dGNz?= =?utf-8?B?NERsSzk3TGxhRDkwR1RJY05CUDRsMEE0TytZTmlOTzZOdllMYmtyUGVPVzdW?= =?utf-8?B?TmZ2TG1TMFd6N1dnS2NhWG5NcUo2MVNiTy9BTElaTkNOZ0tySDBRM0g2c3ZS?= =?utf-8?B?NGNTdmZ3RjJtTk5WQkoyaVVqSVVFK2FPQkp0V3BTM2JQeFd4SFdvS0dhV2hi?= =?utf-8?Q?hT3TdoQgtfePFD4/NyVGzPdKFtE51+54CFSrQ=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(82310400017)(1800799015)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2024 11:09:39.4270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2af04927-393b-4ef0-5b92-08dc79868225 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DD.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9030 For iommu_groups to form correctly, the ACS settings in the PCIe fabric need to be setup early in the boot process, either via the BIOS or via the kernel disable_acs_redir parameter. disable_acs_redir allows clearing the RR|CR|EC ACS flags, but the PCIe spec Rev3.0 already defines 7 different ACS related flags with many more useful combinations depending on the fabric design. For backward compatibility, leave the 'disable_acs_redir' as is and add a new parameter 'config_acs'so that the user can directly specify the ACS flags to set on a per-device basis. Use a similar syntax to the existing 'resource_alignment'  parameter by using the @ character and have the user specify the ACS flags using a bit encoding. If both 'disable_acs_redir' and 'config_acs' are specified for a particular device, configuration specified through 'config_acs' takes precedence over the other. Signed-off-by: Vidya Sagar --- v2: * Refactored the code as per Jason's suggestion .../admin-guide/kernel-parameters.txt | 22 +++ drivers/pci/pci.c | 147 +++++++++++------- 2 files changed, 111 insertions(+), 58 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 41644336e..b4a8207eb 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4456,6 +4456,28 @@ bridges without forcing it upstream. Note: this removes isolation between devices and may put more devices in an IOMMU group. + config_acs= + Format: + =@[; ...] + Specify one or more PCI devices (in the format + specified above) optionally prepended with flags + and separated by semicolons. The respective + capabilities will be enabled, disabled or unchanged + based on what is specified in flags. + ACS Flags is defined as follows + bit-0 : ACS Source Validation + bit-1 : ACS Translation Blocking + bit-2 : ACS P2P Request Redirect + bit-3 : ACS P2P Completion Redirect + bit-4 : ACS Upstream Forwarding + bit-5 : ACS P2P Egress Control + bit-6 : ACS Direct Translated P2P + Each bit can be marked as + ‘0‘ – force disabled + ‘1’ – force enabled + ‘x’ – unchanged. + Note: this may remove isolation between devices + and may put more devices in an IOMMU group. force_floating [S390] Force usage of floating interrupts. nomio [S390] Do not use MIO instructions. norid [S390] ignore the RID field and force use of diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index a607f277c..862df97f1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -887,30 +887,67 @@ void pci_request_acs(void) } static const char *disable_acs_redir_param; +static const char *config_acs_param; -/** - * pci_disable_acs_redir - disable ACS redirect capabilities - * @dev: the PCI device - * - * For only devices specified in the disable_acs_redir parameter. - */ -static void pci_disable_acs_redir(struct pci_dev *dev) +struct pci_acs { + u16 cap; + u16 ctrl; + u16 fw_ctrl; +}; + +static void __pci_config_acs(struct pci_dev *dev, struct pci_acs *caps, + const char *p, u16 mask, u16 flags) { + char *delimit; int ret = 0; - const char *p; - int pos; - u16 ctrl; - if (!disable_acs_redir_param) + if (!p) return; - p = disable_acs_redir_param; while (*p) { + if (!mask) { + /* Check for ACS flags */ + delimit = strstr(p, "@"); + if (delimit) { + int end; + u32 shift = 0; + + end = delimit - p - 1; + + while (end > -1) { + if (*(p + end) == '0') { + mask |= 1 << shift; + shift++; + end--; + } else if (*(p + end) == '1') { + mask |= 1 << shift; + flags |= 1 << shift; + shift++; + end--; + } else if ((*(p + end) == 'x') || (*(p + end) == 'X')) { + shift++; + end--; + } else { + pci_err(dev, "Invalid ACS flags... Ignoring\n"); + return; + } + } + p = delimit + 1; + } else { + pci_err(dev, "ACS Flags missing\n"); + return; + } + } + + if (mask & ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | PCI_ACS_CR | + PCI_ACS_UF | PCI_ACS_EC | PCI_ACS_DT)) { + pci_err(dev, "Invalid ACS flags specified\n"); + return; + } + ret = pci_dev_str_match(dev, p, &p); if (ret < 0) { - pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n", - disable_acs_redir_param); - + pr_info_once("PCI: Can't parse acs command line parameter\n"); break; } else if (ret == 1) { /* Found a match */ @@ -930,56 +967,37 @@ static void pci_disable_acs_redir(struct pci_dev *dev) if (!pci_dev_specific_disable_acs_redir(dev)) return; - pos = dev->acs_cap; - if (!pos) { - pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n"); - return; - } - - pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); + pci_dbg(dev, "ACS mask = 0x%X\n", mask); + pci_dbg(dev, "ACS flags = 0x%X\n", flags); - /* P2P Request & Completion Redirect */ - ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); + /* If mask is 0 then we copy the bit from the firmware setting. */ + caps->ctrl = (caps->ctrl & ~mask) | (caps->fw_ctrl & mask); + caps->ctrl |= flags; - pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); - - pci_info(dev, "disabled ACS redirect\n"); + pci_info(dev, "Configured ACS to 0x%x\n", caps->ctrl); } /** * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities * @dev: the PCI device */ -static void pci_std_enable_acs(struct pci_dev *dev) +static void pci_std_enable_acs(struct pci_dev *dev, struct pci_acs *caps) { - int pos; - u16 cap; - u16 ctrl; - - pos = dev->acs_cap; - if (!pos) - return; - - pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); - pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); - /* Source Validation */ - ctrl |= (cap & PCI_ACS_SV); + caps->ctrl |= (caps->cap & PCI_ACS_SV); /* P2P Request Redirect */ - ctrl |= (cap & PCI_ACS_RR); + caps->ctrl |= (caps->cap & PCI_ACS_RR); /* P2P Completion Redirect */ - ctrl |= (cap & PCI_ACS_CR); + caps->ctrl |= (caps->cap & PCI_ACS_CR); /* Upstream Forwarding */ - ctrl |= (cap & PCI_ACS_UF); + caps->ctrl |= (caps->cap & PCI_ACS_UF); /* Enable Translation Blocking for external devices and noats */ if (pci_ats_disabled() || dev->external_facing || dev->untrusted) - ctrl |= (cap & PCI_ACS_TB); - - pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); + caps->ctrl |= (caps->cap & PCI_ACS_TB); } /** @@ -988,23 +1006,33 @@ static void pci_std_enable_acs(struct pci_dev *dev) */ static void pci_enable_acs(struct pci_dev *dev) { - if (!pci_acs_enable) - goto disable_acs_redir; + struct pci_acs caps; + int pos; + + pos = dev->acs_cap; + if (!pos) + return; - if (!pci_dev_specific_enable_acs(dev)) - goto disable_acs_redir; + pci_read_config_word(dev, pos + PCI_ACS_CAP, &caps.cap); + pci_read_config_word(dev, pos + PCI_ACS_CTRL, &caps.ctrl); + caps.fw_ctrl = caps.ctrl; - pci_std_enable_acs(dev); + /* If an iommu is present we start with kernel default caps */ + if (pci_acs_enable) { + if (pci_dev_specific_enable_acs(dev)) + pci_std_enable_acs(dev, &caps); + } -disable_acs_redir: /* - * Note: pci_disable_acs_redir() must be called even if ACS was not - * enabled by the kernel because it may have been enabled by - * platform firmware. So if we are told to disable it, we should - * always disable it after setting the kernel's default - * preferences. + * Always apply caps from the command line, even if there is no iommu. + * Trust that the admin has a reason to change the ACS settings. */ - pci_disable_acs_redir(dev); + __pci_config_acs(dev, &caps, disable_acs_redir_param, + PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC, + ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC)); + __pci_config_acs(dev, &caps, config_acs_param, 0, 0); + + pci_write_config_word(dev, pos + PCI_ACS_CTRL, caps.ctrl); } /** @@ -7023,6 +7051,8 @@ static int __init pci_setup(char *str) pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS); } else if (!strncmp(str, "disable_acs_redir=", 18)) { disable_acs_redir_param = str + 18; + } else if (!strncmp(str, "config_acs=", 11)) { + config_acs_param = str + 11; } else { pr_err("PCI: Unknown option `%s'\n", str); } @@ -7047,6 +7077,7 @@ static int __init pci_realloc_setup_params(void) resource_alignment_param = kstrdup(resource_alignment_param, GFP_KERNEL); disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL); + config_acs_param = kstrdup(config_acs_param, GFP_KERNEL); return 0; } -- 2.25.1