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Date: Tue, 21 May 2024 14:47:55 +0200
From: Andrew Lunn <andrew@lunn.ch>
To: Larry Chiu <larry.chiu@realtek.com>
Cc: Justin Lai <justinlai0215@realtek.com>,
	"kuba@kernel.org" <kuba@kernel.org>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"edumazet@google.com" <edumazet@google.com>,
	"pabeni@redhat.com" <pabeni@redhat.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"jiri@resnulli.us" <jiri@resnulli.us>,
	"horms@kernel.org" <horms@kernel.org>,
	Ping-Ke Shih <pkshih@realtek.com>
Subject: Re: [PATCH net-next v19 01/13] rtase: Add pci table supported in
 this module
Message-ID: <97e30c5f-1656-46d0-b06c-3607a90ec96f@lunn.ch>
References: <20240517075302.7653-1-justinlai0215@realtek.com>
 <20240517075302.7653-2-justinlai0215@realtek.com>
 <d840e007-c819-42df-bc71-536328d4f5d7@lunn.ch>
 <e5d7a77511f746bdb0b38b6174ef5de4@realtek.com>
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In-Reply-To: <e5d7a77511f746bdb0b38b6174ef5de4@realtek.com>

On Tue, May 21, 2024 at 06:20:04AM +0000, Larry Chiu wrote:
> 
> >> + *  Below is a simplified block diagram of the chip and its relevant interfaces.
> >> + *
> >> + *               *************************
> >> + *               *                       *
> >> + *               *  CPU network device   *
> >> + *               *                       *
> >> + *               *   +-------------+     *
> >> + *               *   |  PCIE Host  |     *
> >> + *               ***********++************
> >> + *                          ||
> >> + *                         PCIE
> >> + *                          ||
> >> + *      ********************++**********************
> >> + *      *            | PCIE Endpoint |             *
> >> + *      *            +---------------+             *
> >> + *      *                | GMAC |                  *
> >> + *      *                +--++--+  Realtek         *
> >> + *      *                   ||     RTL90xx Series  *
> >> + *      *                   ||                     *
> >> + *      *     +-------------++----------------+    *
> >> + *      *     |           | MAC |             |    *
> >> + *      *     |           +-----+             |    *
> >> + *      *     |                               |    *
> >> + *      *     |     Ethernet Switch Core      |    *
> >> + *      *     |                               |    *
> >> + *      *     |   +-----+           +-----+   |    *
> >> + *      *     |   | MAC |...........| MAC |   |    *
> >> + *      *     +---+-----+-----------+-----+---+    *
> >> + *      *         | PHY |...........| PHY |        *
> >> + *      *         +--++-+           +--++-+        *
> >> + *      *************||****************||***********
> >> + *
> >> + *  The block of the Realtek RTL90xx series is our entire chip 
> >> + architecture,
> >> + *  the GMAC is connected to the switch core, and there is no PHY in between.
> >
> >Given this architecture, this driver cannot be used unless there is a switch driver as well. This driver is nearly ready to be merged. So what are your plans for the switch driver? Do you have a first version you can post? That will reassure us you do plan to release a switch driver, and not use a SDK in userspace.
> >
> >        Andrew
> 
> Hi Andrew,
> This GMAC is configured after the switch is boot-up and does not require a switch driver to work.

But if you cannot configure the switch, it is pointless passing the
switch packets. The Linux architecture is that Linux needs to be able
to control the switch somehow. There needs to be a driver with the
switchdev API on its upper side which connects it to the Linux network
stack. Ideally the lower side of this driver can directly write switch
registers. Alternatively it can make some sort of RPC to firmware
which configures the switch.

Before committing this MAC driver, we will want to be convinced there
is a switchdev driver for the switch.

	Andrew