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Peter Anvin" , "Peter Zijlstra (Intel)" , Uros Bizjak , Rick Edgecombe , Arnd Bergmann , Mateusz Guzik , Thomas Renninger , Andi Kleen , linux-kernel@vger.kernel.org, patches@lists.linux.dev Subject: Re: [PATCH v6 16/49] x86/platform/intel-mid: Switch to new Intel CPU model defines Message-ID: References: <20240520224620.9480-1-tony.luck@intel.com> <20240520224620.9480-17-tony.luck@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240520224620.9480-17-tony.luck@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo On Mon, May 20, 2024 at 03:45:47PM -0700, Tony Luck wrote: > New CPU #defines encode vendor and family as well as model. .. > - switch (boot_cpu_data.x86_model) { > - case 0x3C: > - case 0x4A: > + switch (boot_cpu_data.x86_vfm) { > + case INTEL_HASWELL: Thanks, God^W your series, I just realised that this is quite a mistake. I mean, you need to remove this line (with HASWELL) from this file. Fixes: bc20aa48bbb3 ("x86, intel-mid: Add Merrifield platform support") HASWELL was never a part of Intel MID initiative (in a sense how it's organised in HW and FW). > + case INTEL_ATOM_SILVERMONT_MID: > x86_platform.legacy.rtc = 1; > break; So, TL;DR: Please add the patch, I will give a tag to it immediately. -- With Best Regards, Andy Shevchenko