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Date: Tue, 21 May 2024 20:24:50 +0100
From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Da Xue <da@libre.computer>
Cc: Andrew Lunn <andrew@lunn.ch>, Heiner Kallweit <hkallweit1@gmail.com>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Kevin Hilman <khilman@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-stable <stable@vger.kernel.org>
Subject: Re: [PATCH] net: mdio: meson-gxl set 28th bit in eth_reg2
Message-ID: <Zkz1Au7njclh1r3g@shell.armlinux.org.uk>
References: <CACqvRUbx-KsrMwCHYQS6eGXBohynD8Q1CQx=8=9VhqZi13BCQQ@mail.gmail.com>
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Sender: Russell King (Oracle) <linux@armlinux.org.uk>

On Tue, May 21, 2024 at 02:56:45PM -0400, Da Xue wrote:
> @@ -65,7 +66,7 @@ static void gxl_enable_internal_mdio(struct
> gxl_mdio_mux *priv)
>   * The only constraint is that it must match the one in
>   * drivers/net/phy/meson-gxl.c to properly match the PHY.
>   */
> - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
> + writel(REG2_RESERVED_28 | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID),
>          priv->regs + ETH_REG2);
> 
>   /* Enable the internal phy */

In addition to what Andrew said, you need to look at how you're sending
patches - this patch looks like it has been whitespace damaged, which
means it can't be applied.

-- 
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