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[24.150.219.207]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-43df54d85a0sm161723611cf.23.2024.05.21.12.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 May 2024 12:49:20 -0700 (PDT) From: Trevor Gamblin To: linux-pwm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, u.kleine-koenig@pengutronix.de, michael.hennerich@analog.com, nuno.sa@analog.com, tgamblin@baylibre.com, dlechner@baylibre.com Subject: [PATCH 2/2 v3] pwm: axi-pwmgen: add duty offset support Date: Tue, 21 May 2024 15:49:16 -0400 Message-ID: <20240521194916.1897909-3-tgamblin@baylibre.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240521194916.1897909-1-tgamblin@baylibre.com> References: <20240521194916.1897909-1-tgamblin@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Enable duty_offset feature now that it is supported in the pwm subsystem. Related macros and struct fields related to duty_offset are renamed to be consistent. Signed-off-by: Trevor Gamblin --- v3 changes: * rebased on top of latest pwm/for-next v2 changes: * Address feedback for driver in v1: * Remove line setting supports_offset flag in pwm_chip, since that has been removed from the struct in core.c. --- drivers/pwm/pwm-axi-pwmgen.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c index e0bf90cc2ba3..9ae06b105d07 100644 --- a/drivers/pwm/pwm-axi-pwmgen.c +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -56,7 +56,7 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm, struct axi_pwmgen_ddata *ddata = pwmchip_get_drvdata(chip); unsigned int ch = pwm->hwpwm; struct regmap *regmap = ddata->regmap; - u64 period_cnt, duty_cnt; + u64 period_cnt, duty_cnt, duty_offset_cnt; int ret; if (state->polarity != PWM_POLARITY_NORMAL) @@ -81,6 +81,14 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm, ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), duty_cnt); if (ret) return ret; + + duty_offset_cnt = mul_u64_u64_div_u64(state->duty_offset, ddata->clk_rate_hz, NSEC_PER_SEC); + if (duty_offset_cnt > UINT_MAX) + duty_offset_cnt = UINT_MAX; + + ret = regmap_write(regmap, AXI_PWMGEN_CHX_OFFSET(ch), duty_offset_cnt); + if (ret) + return ret; } else { ret = regmap_write(regmap, AXI_PWMGEN_CHX_PERIOD(ch), 0); if (ret) @@ -89,6 +97,10 @@ static int axi_pwmgen_apply(struct pwm_chip *chip, struct pwm_device *pwm, ret = regmap_write(regmap, AXI_PWMGEN_CHX_DUTY(ch), 0); if (ret) return ret; + + ret = regmap_write(regmap, AXI_PWMGEN_CHX_OFFSET(ch), 0); + if (ret) + return ret; } return regmap_write(regmap, AXI_PWMGEN_REG_CONFIG, AXI_PWMGEN_LOAD_CONFIG); @@ -117,6 +129,12 @@ static int axi_pwmgen_get_state(struct pwm_chip *chip, struct pwm_device *pwm, state->duty_cycle = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); + ret = regmap_read(regmap, AXI_PWMGEN_CHX_OFFSET(ch), &cnt); + if (ret) + return ret; + + state->duty_offset = DIV_ROUND_UP_ULL((u64)cnt * NSEC_PER_SEC, ddata->clk_rate_hz); + state->polarity = PWM_POLARITY_NORMAL; return 0; -- 2.45.1