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(unknown [IPv6:240e:358:11a2:a00:dc73:854d:832e:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id D088C1A3FBD; Tue, 21 May 2024 22:07:31 -0400 (EDT) From: Xi Ruoyao To: Dave Hansen , Michael Kelley , Pawan Gupta Cc: Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, Xi Ruoyao , Sean Christopherson , Andrew Cooper Subject: [PATCH v10 2/2] x86/mm: Don't disable PCID if the kernel is running on a hypervisor Date: Wed, 22 May 2024 10:06:25 +0800 Message-ID: <20240522020625.69418-2-xry111@xry111.site> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240522020625.69418-1-xry111@xry111.site> References: <20240522020625.69418-1-xry111@xry111.site> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Intel erratum for "incomplete Global INVLPG flushes" says: This erratum does not apply in VMX non-root operation. It applies only when PCIDs are enabled and either in VMX root operation or outside VMX operation. So if the kernel is running in a hypervisor, we are in VMX non-root operation and we should be safe to use PCID. Cc: Dave Hansen Cc: Michael Kelley Cc: Pawan Gupta Cc: Sean Christopherson Cc: Andrew Cooper Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@tip-bot2/ Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24 Signed-off-by: Xi Ruoyao --- arch/x86/mm/init.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index e960196e8058..1efd55835fc5 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -279,7 +279,7 @@ static const struct x86_cpu_id invlpg_miss_ids[] = { static void setup_pcid(void) { - const struct x86_cpu_id *invlpg_miss_match; + const struct x86_cpu_id *invlpg_miss_match = NULL; if (!IS_ENABLED(CONFIG_X86_64)) return; @@ -287,7 +287,9 @@ static void setup_pcid(void) if (!boot_cpu_has(X86_FEATURE_PCID)) return; - invlpg_miss_match = x86_match_cpu(invlpg_miss_ids); + /* Only bare-metal is affected. PCIDs in guests are OK. */ + if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) + invlpg_miss_match = x86_match_cpu(invlpg_miss_ids); if (invlpg_miss_match && boot_cpu_data.microcode < invlpg_miss_match->driver_data) { -- 2.45.1