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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?MnRHaUhGMEFmQ3AySzRLNTUzZ05PRGtUazNScEp6T3hhTERLdDRlbGFvdXJn?= =?utf-8?B?M3dyMjBWTkVPMnFFVnliV2R1SzVaOFVqL3kzRHNVK1VpSFBLSURtd2lIcXFz?= =?utf-8?B?M3JDa1l6MU5KR1F4b01xbXpXU01PZkMyYjdiWVBIMUdLU05nZ3lsQUJJa2dR?= =?utf-8?B?M1o2QzRUU214NGh5WVdJQkNUY2tQdSt6dURRQkh5QnZOcG8zOG9icXJYTEhV?= =?utf-8?B?T3licW5SZ2pBei84NEtnMktJUGdwQ2pvZnpodmZzVFQ3dmgrY2VGTFBMdFRB?= =?utf-8?B?ZDRRRlVjOFJVckR4OVI1U01SWk56aXFmc1ozQ3JyUWxvcVJzaUdmVkJ3RlJ1?= =?utf-8?B?cEVVdGJMWUxCR3M0ajR2dFAvUUVvQXgyOFQ1YU96Ly9INndaUFluZVlzaFly?= =?utf-8?B?U3VyMjE1ODIwY3huM1o5Ly9LUGNlYlRTRmtZbHpiSnRnbVJKaGM2ck9NSDds?= =?utf-8?B?KzZkOFR2Qk0xbWlVTGEzRjlsSjNMam55aGJOTEkyOUFaUU5YS2FQTUQ1TWxH?= =?utf-8?B?Rm1hbmYza05jNWo3UnoyamVRU2lHbTIrNGhnRnhndWE5bk9HcHRMMkR2RlZp?= =?utf-8?B?RU9lb29zcGJsV3Byd05KL3NuN29HRkVxWDkrNnk1cUk2N0FaLzBlcTB5NWor?= =?utf-8?B?aU03UjNIWHR1dWI0bmFjcGFycW5xS3lYM1dNb001bTlLblNsREVOMThLY2lX?= =?utf-8?B?UzdpdWcxQk9pZWxDajRIVUFqS2VNOG1jQTcyQU5PQU1FelZEVWxOQjJtTlB0?= =?utf-8?B?aFFseTdjK0lNTWVBdHBuendicFVSa203SmdXd2FacUF2K1pSMzJySFdsaWFE?= =?utf-8?B?YXhEeXJVN0xWZm5nb09vRW5jYmU3YmRsb0llR0tweTV2bVk4aU1ZcUZXejlW?= =?utf-8?B?OWJJL3F0NldwazllUzFib0JLUUcrSllZVTVtdXE1VHM2YUZzODhJTU5JYjZs?= =?utf-8?B?Wll1UlEzbUZnbXdlbVpTaFo2dHIyMFhOdGtxOWdsYkJoZ0VyTDdES3F0REVn?= =?utf-8?B?WHU3MUhaM1EvQnhIcWQrM1p0Y1A3UjljS21jL2xEWEkyaS9Jd0NPbkZpdUts?= =?utf-8?B?STFhNHMyUG9Bc20vVmFuVW1GWlk1T2hFY2xNM2lVOEQ3bFN4Zml4Qkh5eFhx?= =?utf-8?B?cFpnV29KRWF0MlQzTVZjU3pqTEE0SjFzZEp0SmVvQjZWeStFZ2NvaXoremhj?= =?utf-8?B?c2xsZS8wa0RUcGxGeGR5TXo2WVlsTXJuZ1RBNjFzd2tMM3dlODlFQTZxZkJ1?= =?utf-8?B?NlB4eC9JK1hCVUpVK1QrV1UrY2VpdVNObUJJTmdxUEllNVRoV1BGby9UTjlC?= =?utf-8?B?RnpUZm9SVlJJR1h0RlRmaGNUN29GRG81UVc0Z2UwSy90U3FBMkgzNXZPQjdD?= =?utf-8?B?KytMcS8xcnB6Mi9JbzA0NGpnNEx1R1BrR0VVbEc0dXdtWTgvTVB2OUQ4SmJq?= =?utf-8?B?RkdZVzVYeVhqUTBKaTcrWnQ0bFVSU3RpZ01PYS9TUkptM3g1TDZKQ2VtbmpO?= =?utf-8?B?TmVTM0VFczRneklneVFJcmlrQ2VvR21XUXNEU3g1RmszdEgrZ0w4Vy9paEpM?= =?utf-8?B?MUd4bjQyM0ErQzZ2R21EVUVDbUhSUmRMRGs2WndIalBrTzNiaURMY3cvTHY1?= =?utf-8?B?d01Fbm8xQmFHeEUxTjA1emJxLzB1YkgwZlEvK0t3MnJaVHN2QkwvbHFKMHRM?= =?utf-8?B?TVJpbUxiNE9EU3NYQ2ZFL2FTVHFHd3ZhN0RrUUxwK0planlZZ1VVVHFSU05S?= =?utf-8?B?eENpUGJsMkI1Tk9KQVlJVm9UaTRqdkZSbGhXdXZQQmw4OUV3VkhaY1pNNmxa?= =?utf-8?B?RUVYNkpHWkRCUDhJZkhZMnBwVk50ZStoaUVXaVFOaXo1TFhjRzYwYW94VDc4?= =?utf-8?B?Yyt3OGw2Y3F5RWQ0RWpzSkRXcGtscDY2ZkZRMUl2OENyOE01czRRTVJwUmZa?= =?utf-8?B?cDZDNzhObHdxWFBFMmxpV0NsbGhXRjZtTVU0cEMveHNXWHpqNXJsc3gzV0Mr?= =?utf-8?B?d1VjL01Ld2hTc1NzMTlqQmNxK1hXOG1Tb3dTdG9Nd1NUY0VycXFsdnNpdFJ0?= =?utf-8?B?NE15ZDdwcEtmTzFkRXZoM2JOa3l3VGN2MGRObjhHS3dIaERFMVorUUNKUHc2?= =?utf-8?Q?e+0jCyvNy7iss6Ym+h1qgZhKp?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: ea078936-f1a5-400e-ed2e-08dc7a21064a X-MS-Exchange-CrossTenant-AuthSource: CY8PR12MB7706.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 May 2024 05:35:43.9369 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jfnsqdYALXkcSAaW0FQhy7X1VStaH6eO3XSb53AZyQwWejOXa2PNj9yFNMOaYWFuDeoJIm52X16dUeyySEcHlw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8487 On 21-05-2024 17:23, Krzysztof Kozlowski wrote: > On 21/05/2024 13:08, Sameer Pujar wrote: >> From: Mohan Kumar >> >> For Non-Hypervisor mode, Tegra ADMA driver requires the register >> resource range to include both global and channel page in the reg >> entry. For Hypervisor more, Tegra ADMA driver requires only the >> channel page and global page range is not allowed for access. >> >> Add reg-names DT binding for Hypervisor mode to help driver to >> differentiate the config between Hypervisor and Non-Hypervisor >> mode of execution. >> >> Signed-off-by: Mohan Kumar >> Signed-off-by: Sameer Pujar >> --- >> .../devicetree/bindings/dma/nvidia,tegra210-adma.yaml | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml >> index 877147e95ecc..ede47f4a3eec 100644 >> --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml >> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml >> @@ -29,8 +29,18 @@ properties: >> - const: nvidia,tegra186-adma >> >> reg: >> + description: | >> + For hypervisor mode, the address range should include a >> + ADMA channel page address range, for non-hypervisor mode >> + it starts with ADMA base address covering Global and Channel >> + page address range. >> maxItems: 1 >> >> + reg-names: >> + description: only required for Hypervisor mode. > This does not work like that. I provide vm entry for non-hypervisor mode > and what? You claim it is virtualized? > > Drop property. With 'vm' entry added for hypervisor mode, the 'reg' address range needs to be updated to use channel specific region only. This is used to inform driver to skip global regions which is taken care by hypervisor. This is expected to be used in the scenario where Linux acts as a virtual machine (VM). May be the hypervisor mode gives a different impression here? Sorry, I did not understand what dropping the property exactly means here.