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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Il 22/05/24 06:43, Sergio Paracuellos ha scritto: > MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) with 3 Root > Ports. Add PCIe host topology ascii graph to the binding for completeness. > > Suggested-by: Krzysztof Kozlowski > Signed-off-by: Sergio Paracuellos Lovely. Reviewed-by: AngeloGioacchino Del Regno > --- > .../bindings/pci/mediatek,mt7621-pcie.yaml | 29 +++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml > index 6fba42156db6..c41608863d6c 100644 > --- a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml > @@ -13,6 +13,35 @@ description: |+ > MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) > with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link > > + MT7621 PCIe HOST Topology > + > + .-------. > + | | > + | CPU | > + | | > + '-------' > + | > + | > + | > + v > + .------------------. > + .-----------| HOST/PCI Bridge |------------. > + | '------------------' | Type1 > + BUS0 | | | Access > + v v v On Bus0 > + .-------------. .-------------. .-------------. > + | VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P | > + | BUS0 | | BUS0 | | BUS0 | > + | DEV0 | | DEV1 | | DEV2 | > + '-------------' '-------------' '-------------' > + Type0 | Type0 | Type0 | > + Access BUS1 | Access BUS2| Access BUS3| > + On Bus1 v On Bus2 v On Bus3 v > + .----------. .----------. .----------. > + | Device 0 | | Device 0 | | Device 0 | > + | Func 0 | | Func 0 | | Func 0 | > + '----------' '----------' '----------' > + > allOf: > - $ref: /schemas/pci/pci-host-bridge.yaml# >