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Wed, 22 May 2024 08:40:01 +0000 Received: from BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::b576:d3bd:c8e0:4bc1]) by BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::b576:d3bd:c8e0:4bc1%5]) with mapi id 15.20.7611.016; Wed, 22 May 2024 08:40:00 +0000 From: "Tian, Kevin" To: Nicolin Chen , "will@kernel.org" , "robin.murphy@arm.com" , "jgg@nvidia.com" , "suravee.suthikulpanit@amd.com" CC: "joro@8bytes.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "Liu, Yi L" , "eric.auger@redhat.com" , "vasant.hegde@amd.com" , "jon.grimm@amd.com" , "santosh.shukla@amd.com" , "Dhaval.Giani@amd.com" , "shameerali.kolothum.thodi@huawei.com" Subject: RE: [PATCH RFCv1 00/14] Add Tegra241 (Grace) CMDQV Support (part 2/2) Thread-Topic: [PATCH RFCv1 00/14] Add Tegra241 (Grace) CMDQV Support (part 2/2) Thread-Index: AQHajVVgzSKGnSPg+UW1Z+6EC5j/q7GjLESA Date: Wed, 22 May 2024 08:40:00 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c60ced56-02f2-4c31-e3a3-08dc7a3ac4d4 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 May 2024 08:40:00.8273 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 8Sbxg1YQIUN6YQw7rv2uiR3dn1rS2WLs62ChUt/xHxp4soow14y4z6SCI/1G0UrT5QG1TdFxBBzdcpVtDZyhSQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB8198 X-OriginatorOrg: intel.com > From: Nicolin Chen > Sent: Saturday, April 13, 2024 11:47 AM >=20 > This is an experimental RFC series for VIOMMU infrastructure, using NVIDI= A > Tegra241 (Grace) CMDQV as a test instance. >=20 > VIOMMU obj is used to represent a virtual interface (iommu) backed by an > underlying IOMMU's HW-accelerated feature for virtualizaion: for example, > NVIDIA's VINTF (v-interface for CMDQV) and AMD"s vIOMMU. >=20 > VQUEUE obj is used to represent a virtual command queue (buffer) backed > by > an underlying IOMMU command queue to passthrough for VMs to use > directly: > for example, NVIDIA's Virtual Command Queue and AMD's Command Buffer. >=20 is VCMDQ more accurate? AMD also supports fault queue passthrough then VQUEUE sounds broader than a cmd queue...