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[209.85.128.173]) by smtp.gmail.com with ESMTPSA id 00721157ae682-6209e346810sm58078907b3.95.2024.05.22.03.19.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 May 2024 03:19:43 -0700 (PDT) Received: by mail-yw1-f173.google.com with SMTP id 00721157ae682-61be4b98766so7421587b3.3; Wed, 22 May 2024 03:19:43 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCWA7Z1co0zWrNN6AU0xCnH0fn9bQaTfVokExwTEkX5jgSw39pkc1gdjTocc2lc+5wTtSHd3t1i0xokoe9vejM5QF3rKWJJLetTEc2ADe4HtQZM+ncOcczb5Pp/w00sGw/g+O7tIpZySSwZsxm/mPIvjrfZahI6oZTWtg3d3YbQweHw6Ub+wueMvmeWq0RYoNCfyArsFW9MaAVHOh8OY1x+Gpji2K5czsw== X-Received: by 2002:a0d:cc4a:0:b0:61a:999f:e499 with SMTP id 00721157ae682-627e471f818mr15049237b3.22.1716373183070; Wed, 22 May 2024 03:19:43 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240423175900.702640-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240423175900.702640-4-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20240423175900.702640-4-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 22 May 2024 12:19:31 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 03/13] pinctrl: renesas: pinctrl-rzg2l: Allow more bits for pin configuration To: Prabhakar Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Prabhakar, On Tue, Apr 23, 2024 at 7:59=E2=80=AFPM Prabhakar wrote: > From: Lad Prabhakar > > The pin configuration bits have been growing for every new SoCs being > added for the pinctrl-rzg2l driver which would mean updating the macros > every time for each new configuration. To avoid this allocate additional > bits for pin configuration by relocating the known fixed bits to the very > end of the configuration. > > Also update the size of 'cfg' to 'u64' to allow more configuration bits i= n > the 'struct rzg2l_variable_pin_cfg'. > > Signed-off-by: Lad Prabhakar > --- > RFC->v2 > - Merged the macros and rzg2l_variable_pin_cfg changes into single patch > - Updated types for the config changes Thanks for the update! > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -78,9 +78,9 @@ > PIN_CFG_FILNUM | \ > PIN_CFG_FILCLKSEL) > > -#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) > -#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) > -#define PIN_CFG_MASK GENMASK(19, 0) > +#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) > +#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47) > +#define PIN_CFG_MASK GENMASK_ULL(46, 0) > > /* > * m indicates the bitmap of supported pins, a is the register index > @@ -241,9 +241,9 @@ struct rzg2l_dedicated_configs { > * @pin: port pin > */ > struct rzg2l_variable_pin_cfg { > - u32 cfg:20; > - u32 port:5; > - u32 pin:3; > + u64 cfg:46; 47, to match PIN_CFG_MASK()? > + u64 port:5; > + u64 pin:3; > }; To avoid such mistakes, and to increase uniformity, I think it would be good to get rid of this structure, and replace it by masks, to be used with FIELD_GET() and FIELD_PREP_CONST(). Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds