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Wed, 22 May 2024 10:56:49 GMT Received: from [10.216.17.165] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 22 May 2024 03:56:45 -0700 Message-ID: <40594542-ac60-0ff7-8474-a93f678a99be@quicinc.com> Date: Wed, 22 May 2024 16:26:41 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v4 2/7] ASoC: codecs: wcd937x-sdw: add SoundWire driver Content-Language: en-US To: Mark Brown CC: Srinivas Kandagatla , Banajit Goswami , Liam Girdwood , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , , , , , , , References: <20240516044801.1061838-1-quic_mohs@quicinc.com> <20240516044801.1061838-3-quic_mohs@quicinc.com> <91f581ef-58ea-4b98-80e2-dd9b14a61c60@sirena.org.uk> From: Mohammad Rafi Shaik In-Reply-To: <91f581ef-58ea-4b98-80e2-dd9b14a61c60@sirena.org.uk> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: oEa4VcuMEe6-HxUvq2uT8Hl8_qXlruDv X-Proofpoint-GUID: oEa4VcuMEe6-HxUvq2uT8Hl8_qXlruDv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-22_05,2024-05-22_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 malwarescore=0 spamscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 suspectscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405010000 definitions=main-2405220074 On 5/16/2024 5:17 PM, Mark Brown wrote: > On Thu, May 16, 2024 at 10:17:56AM +0530, Mohammad Rafi Shaik wrote: > >> +static const struct reg_default wcd937x_defaults[] = { > >> + { WCD937X_DIGITAL_EFUSE_REG_0, 0x00 }, >> + { WCD937X_DIGITAL_EFUSE_REG_1, 0xff }, >> + { WCD937X_DIGITAL_EFUSE_REG_2, 0xff }, >> + { WCD937X_DIGITAL_EFUSE_REG_3, 0xff }, > > Given the name I'd expect these to vary per device so not have default > values. In general ID, status or volatile registers probably shouldn't > have defaults since they should be read from the device. > Thanks for the review, Will cleanup those. >> +static bool wcd937x_readonly_register(struct device *dev, unsigned int reg) >> +{ >> + switch (reg) { > >> + case WCD937X_DIGITAL_CHIP_ID0: >> + case WCD937X_DIGITAL_CHIP_ID1: >> + case WCD937X_DIGITAL_CHIP_ID2: >> + case WCD937X_DIGITAL_CHIP_ID3: > >> + case WCD937X_DIGITAL_EFUSE_REG_0: >> + case WCD937X_DIGITAL_EFUSE_REG_1: >> + case WCD937X_DIGITAL_EFUSE_REG_2: > >> + .readable_reg = wcd937x_readable_register, >> + .writeable_reg = wcd937x_rdwr_register, >> + .volatile_reg = wcd937x_readonly_register, > > It's not a bug per se since things will work but you should probably > have separate volatile and read only checks, things like the ID and > efuse registers are read only but they shouldn't vary at runtime so > could be cached and not volatile. ACK, Will cleanup and improve. Thanks & Regards, Rafi.