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[209.85.128.177]) by smtp.gmail.com with ESMTPSA id 00721157ae682-6209e349e0csm57584897b3.79.2024.05.22.05.23.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 May 2024 05:23:28 -0700 (PDT) Received: by mail-yw1-f177.google.com with SMTP id 00721157ae682-622f5a0badcso53352027b3.2; Wed, 22 May 2024 05:23:28 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCW0+faY9Jv9zLzZjN7oQ3/0W6P9d6ht2FfZWpsObD48dpgqj6oPecan7q046t5AgfVWYEYu7GGu2Y82braQlUXxjFC3Qml+Y/NEDEKW2o20k/6xB68ea6lMpBTO5TCEMLSiu73YMNX476fHosAdxg5o0NI0KgdXoBECbdt/d0lKbuPCrX5bAl3wg/WV7EHe6oc2/llq4mnBszf03ODt6BdNuo4WWGDhqQ== X-Received: by 2002:a05:690c:60c7:b0:627:a382:a0fa with SMTP id 00721157ae682-627e4880150mr20956997b3.52.1716380608278; Wed, 22 May 2024 05:23:28 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240423175900.702640-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240423175900.702640-7-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Wed, 22 May 2024 14:23:15 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 06/13] pinctrl: renesas: pinctrl-rzg2l: Add function pointers for locking/unlocking the PFC register To: Biju Das Cc: Prabhakar , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , "linux-renesas-soc@vger.kernel.org" , "linux-gpio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Fabrizio Castro , Prabhakar Mahadev Lad Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Biju, On Tue, Apr 23, 2024 at 8:12=E2=80=AFPM Biju Das wrote: > > -----Original Message----- > > From: Prabhakar > > Sent: Tuesday, April 23, 2024 6:59 PM > > Subject: [PATCH v2 06/13] pinctrl: renesas: pinctrl-rzg2l: Add function= pointers for > > locking/unlocking the PFC register > > > > From: Lad Prabhakar > > > > On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers. > > However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit contro= ls writing to both PFC and > > PMC registers. Additionally, BIT(7) B0WI is undocumented for the PWPR r= egister on RZ/V2H(P) SoC. To > > accommodate these differences across SoC variants, introduce the set_pf= c_mode() and > > pm_set_pfc() function pointers. > > > > Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_unlock() call is now= called before PMC > > read/write and pwpr_pfc_lock() call is now called after PMC read/write = this is to keep changes > > minimal for RZ/V2H(P). > > > > Signed-off-by: Lad Prabhakar > > --- > > RFC->v2 > > - Introduced function pointer for (un)lock > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > > @@ -2688,6 +2699,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = =3D { > > .variable_pin_cfg =3D r9a07g043f_variable_pin_cfg, > > .n_variable_pin_cfg =3D ARRAY_SIZE(r9a07g043f_variable_pin_cfg), > > #endif > > + .pwpr_pfc_unlock =3D &rzg2l_pwpr_pfc_unlock, > > + .pwpr_pfc_lock =3D &rzg2l_pwpr_pfc_lock, > > }; > > > > static struct rzg2l_pinctrl_data r9a07g044_data =3D { @@ -2699,6 +2712= ,8 @@ static struct > > rzg2l_pinctrl_data r9a07g044_data =3D { > > .n_dedicated_pins =3D ARRAY_SIZE(rzg2l_dedicated_pins.common) + > > ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), > > .hwcfg =3D &rzg2l_hwcfg, > > + .pwpr_pfc_unlock =3D &rzg2l_pwpr_pfc_unlock, > > + .pwpr_pfc_lock =3D &rzg2l_pwpr_pfc_lock, > > }; > > > > static struct rzg2l_pinctrl_data r9a08g045_data =3D { @@ -2709,6 +2724= ,8 @@ static struct > > rzg2l_pinctrl_data r9a08g045_data =3D { > > .n_port_pins =3D ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_= PER_PORT, > > .n_dedicated_pins =3D ARRAY_SIZE(rzg3s_dedicated_pins), > > .hwcfg =3D &rzg3s_hwcfg, > > + .pwpr_pfc_unlock =3D &rzg2l_pwpr_pfc_unlock, > > + .pwpr_pfc_lock =3D &rzg2l_pwpr_pfc_lock, > > Some memory can be saved by avoiding duplication of data by using > a single pointer for structure containing function pointers?? > > struct rzg2l_pinctrl_fns { > void (*pwpr_pfc_unlock)(struct rzg2l_pinctrl *pctrl); > void (*pwpr_pfc_lock)(struct rzg2l_pinctrl *pctrl); > } So that would replace 3 (4 after adding RZ/V2H support) x 2 pointers in rzg2l_pinctrl_data structures by 3 (4) pointers in rzg2l_pinctrl_data structures + 1 (2) x 2 pointers in rzg2l_pinctrl_fns structures, and code size would increase due to extra pointer dereferences before each call. Am I missing something? Merging rzg2l_pwpr_pfc_{,un}lock() into a single function (taking a "bool lock" flag) might be a better solution to reduce rzg2l_pinctrl_data s= ize. Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds