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Message-ID: <6a4767b5-1e2f-dbec-58ca-c44eb0fca6f1@linux.intel.com>
Date: Wed, 22 May 2024 16:40:56 +0300
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To: Daehwan Jung <dh10.jung@samsung.com>,
 Mathias Nyman <mathias.nyman@intel.com>,
 Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: "open list:USB XHCI DRIVER" <linux-usb@vger.kernel.org>,
 open list <linux-kernel@vger.kernel.org>,
 Thinh Nguyen <Thinh.Nguyen@synopsys.com>
References: <CGME20240522010409epcas2p457b2fcb4f423f2500305053f44ae3199@epcas2p4.samsung.com>
 <1716339839-44022-1-git-send-email-dh10.jung@samsung.com>
From: Mathias Nyman <mathias.nyman@linux.intel.com>
Subject: Re: [RFC] usb: host: xhci-mem: Write high first on erst base of
 secondary interrupter
In-Reply-To: <1716339839-44022-1-git-send-email-dh10.jung@samsung.com>
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On 22.5.2024 4.03, Daehwan Jung wrote:
> ERSTBA_HI should be written first on secondary interrupter.
> That's why secondary interrupter could be set while Host Controller
> is already running.
> 
> [Synopsys]- The host controller was design to support ERST setting
> during the RUN state. But since there is a limitation in controller
> in supporting separate ERSTBA_HI and ERSTBA_LO programming,
> It is supported when the ERSTBA is programmed in 64bit,
> or in 32 bit mode ERSTBA_HI before ERSTBA_LO

xHCI specification 5.1 "Register Conventions "states that 64 bit
registers should be written in low-high order

> 
> [Synopsys]- The internal initialization of event ring fetches
> the "Event Ring Segment Table Entry" based on the indication of
> ERSTBA_LO written.
> 

Any idea if this is a common issue with this host?
Should other 64 bit registers also be written in reverse order.

> Signed-off-by: Daehwan Jung <dh10.jung@samsung.com>
> ---
>   drivers/usb/host/xhci-mem.c | 5 ++++-
>   drivers/usb/host/xhci.h     | 6 ++++++
>   2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
> index 3100219..36ee704 100644
> --- a/drivers/usb/host/xhci-mem.c
> +++ b/drivers/usb/host/xhci-mem.c
> @@ -2325,7 +2325,10 @@ xhci_add_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
>   	erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
>   	erst_base &= ERST_BASE_RSVDP;
>   	erst_base |= ir->erst.erst_dma_addr & ~ERST_BASE_RSVDP;
> -	xhci_write_64(xhci, erst_base, &ir->ir_set->erst_base);
> +	if (intr_num == 0)
> +		xhci_write_64(xhci, erst_base, &ir->ir_set->erst_base);
> +	else
> +		xhci_write_64_r(xhci, erst_base, &ir->ir_set->erst_base);

This may cause issues with other hosts expecting low-high order as stated
in the specification.

If all 64 bit registers should be written in high-low order for this host then
maybe set a quirk flag and change xhci_write_64()instead.

xhci_write_64(...)
{
	if (xhci->quirks & XHCI_WRITE_64_HI_LO)
		hi_lo_writeq(val, regs);
	else
		lo_hi_writeq(val, regs);
}
	

Thanks
Mathias