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AJvYcCUMAkpDejiC5haNC0vB+DH6+xsIR5w2EfJ7ri4kJ/rFILUBPqSqGgMZVycnd2132HR+3ybG2XxLBHKRdy1NwbxDIPgmWb0oxlXwN7AFic3ep+/NNl/gn6mfHitZb+sFuDKJJ7DwOG+sRQ== X-Gm-Message-State: AOJu0Yy5ltptS2bwL4YaMrEasqnF9kmkkSgvWw8JOdmDfDwx6y0Btv14 5xMO1Hl9Bj+Vun4Y7N8gefdH+TtY0u4zj0F9QMxuidrrcTyINrrj X-Received: by 2002:a17:90a:8d16:b0:2bd:92e7:e085 with SMTP id 98e67ed59e1d1-2bd9f46e390mr2242146a91.19.1716392340301; Wed, 22 May 2024 08:39:00 -0700 (PDT) Received: from localhost.localdomain ([223.178.84.74]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-2b628ea59absm25574077a91.47.2024.05.22.08.38.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 May 2024 08:38:59 -0700 (PDT) From: Kanak Shilledar X-Google-Original-From: Kanak Shilledar To: Cc: Kanak Shilledar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v2 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc Date: Wed, 22 May 2024 21:08:34 +0530 Message-Id: <20240522153835.22712-1-kanakshilledar111@protonmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series of patches converts the RISC-V CPU interrupt controller to the newer dt-schema binding. Patch 1: This patch is currently at v3 as it has been previously rolled out. Contains the bindings for the interrupt controller. Patch 2: This patch is currently at v2. Contains the reference to the above interrupt controller. Thus, making all the RISC-V interrupt controller bindings in a centralized place. These patches are interdependent. Kanak Shilledar (2): dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema dt-bindings: riscv: cpus: add ref to interrupt-controller .../interrupt-controller/riscv,cpu-intc.txt | 52 ------------- .../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++ .../devicetree/bindings/riscv/cpus.yaml | 21 +----- 3 files changed, 74 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23 -- 2.34.1