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Date: Wed, 22 May 2024 19:26:55 +0100
From: Conor Dooley <conor@kernel.org>
To: Kanak Shilledar <kanakshilledar@gmail.com>
Cc: Kanak Shilledar <kanakshilledar111@protonmail.com>,
	Thomas Gleixner <tglx@linutronix.de>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Samuel Holland <samuel.holland@sifive.com>,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc
Message-ID: <20240522-customs-jaws-d0c792b274b4@spud>
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On Wed, May 22, 2024 at 10:11:20PM +0530, Kanak Shilledar wrote:
> Hi Conor,
>=20
> On Wed, May 22, 2024 at 9:34=E2=80=AFPM Conor Dooley <conor@kernel.org> w=
rote:
> >
> > On Wed, May 22, 2024 at 09:08:34PM +0530, Kanak Shilledar wrote:
> > > This series of patches converts the RISC-V CPU interrupt controller to
> > > the newer dt-schema binding.
> > >
> > > Patch 1:
> > > This patch is currently at v3 as it has been previously rolled out.
> > > Contains the bindings for the interrupt controller.
> > >
> > > Patch 2:
> > > This patch is currently at v2.
> > > Contains the reference to the above interrupt controller. Thus, making
> > > all the RISC-V interrupt controller bindings in a centralized place.o
> >
> > Don't do this, it breaks tooling:
> >
> >         b4 shazam 20240522153835.22712-2-kanakshilledar111@protonmail.c=
om
> >         Grabbing thread from lore.kernel.org/all/20240522153835.22712-2=
-kanakshilledar111@protonmail.com/t.mbox.gz
> >         Checking for newer revisions
> >         Grabbing search results from lore.kernel.org
> >         Analyzing 3 messages in the thread
> >         Looking for additional code-review trailers on lore.kernel.org
> >         Will use the latest revision: v3
> >         You can pick other revisions using the -vN flag
> >         Checking attestation on all messages, may take a moment...
> >         Retrieving CI status, may take a moment...
> >         ---
> >           =E2=9C=93 [PATCH v3 1/2] dt-bindings: interrupt-controller: r=
iscv,cpu-intc: convert to dtschema
> >             =E2=9C=93 Signed: DKIM/gmail.com
> >             + Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >           ERROR: missing [2/2]!
> >         ---
> >         Total patches: 1
> >         ---
> >         WARNING: Thread incomplete!
> >          Base: using specified base-commit 20cb38a7af88dc40095da7c2c909=
4da3873fea23
> >         Applying: dt-bindings: interrupt-controller: riscv,cpu-intc: co=
nvert to dtschema
> >
> > If you change one patch in a series, the whole series gets a new versio=
n.
> > Just let git format-patch do that for you with the "-v N" argument and
> > you'll not have to worry about breaking people's tooling.
>=20
> Sorry for the tooling breaking. I used the "-v N" argument to make the
> v2 patches but I bumped up the "riscv,cpu-intc"patch
> to v3 due to it being in v3 already and it gave errors in the previous
> patchset and you mentioned that I missed the v3 in subject line.
> How shall I proceed with this version mismatch? Shall I make the
> patchset as v3 and have both the patches at v3?

I would make it "RESEND v3".

> > Patches themselves are
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>=20
> I shall include this in my commit message. Is it required to bump the
> version of the patch just for the reviewed flag?

Usually there's no need to resend patches for tags alone. Some people
treat tag-only resubmissions as a "RESEND vN" and others as "vN+1". The
latter is less likely to upset anyone.

Cheers,
Conor.

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