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Thu, 23 May 2024 05:44:40 +0000 Received: from BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::b576:d3bd:c8e0:4bc1]) by BN9PR11MB5276.namprd11.prod.outlook.com ([fe80::b576:d3bd:c8e0:4bc1%5]) with mapi id 15.20.7611.016; Thu, 23 May 2024 05:44:40 +0000 From: "Tian, Kevin" To: Nicolin Chen , Jason Gunthorpe CC: "will@kernel.org" , "robin.murphy@arm.com" , "suravee.suthikulpanit@amd.com" , "joro@8bytes.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-tegra@vger.kernel.org" , "Liu, Yi L" , "eric.auger@redhat.com" , "vasant.hegde@amd.com" , "jon.grimm@amd.com" , "santosh.shukla@amd.com" , "Dhaval.Giani@amd.com" , "shameerali.kolothum.thodi@huawei.com" Subject: RE: [PATCH RFCv1 07/14] iommufd: Add viommu set/unset_dev_id ops Thread-Topic: [PATCH RFCv1 07/14] iommufd: Add viommu set/unset_dev_id ops Thread-Index: AQHajVVq/X0HjqCDvU+a/LkdwhCQ/LGT28sAgADojoCAD8kmgA== Date: Thu, 23 May 2024 05:44:40 +0000 Message-ID: References: <6e57d7b5aa1705bdd547b1cd2aca93d3bf70dfa4.1712978212.git.nicolinc@nvidia.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR11MB5276.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e1525e81-6f2e-4fbc-1f3c-08dc7aeb709a X-MS-Exchange-CrossTenant-originalarrivaltime: 23 May 2024 05:44:40.4604 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: emBmnH+sQ/lh/h25mVOlRFFy/NapD378PL9FAQzhSyOXhNuzOuzGg0gCOfQmqgb/yNbevIu+wZEgZYUa5D2hHw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB7927 X-OriginatorOrg: intel.com > From: Nicolin Chen > Sent: Monday, May 13, 2024 12:39 PM >=20 > On Sun, May 12, 2024 at 11:46:54AM -0300, Jason Gunthorpe wrote: > > On Fri, Apr 12, 2024 at 08:47:04PM -0700, Nicolin Chen wrote: > > > Add a pair of ops to set and unet device's virtual ID that belongs to > > > a viommu object. They will be used, in the following patch, by iommuf= d > > > to support some HW-acceleration feature from the host level. > > > > > > For instance, every device behind an ARM SMMU has a Stream ID. The ID > > > is used by ATC invalidation commands so SMMU HW can direct > invalidation > > > requests to the corresponding PCI device where the ID belongs to. In = a > > > virtualization use case, a passthroughed device in the VM will have a > > > virtuail Stream ID, used by the ATC invalidation commands in the gues= t > > > system. NVIDIA's CMDQV extension for SMMUv3 provides a v-interface > to > > > execute the guest-level ATC invalidation commands directly, yet needs > > > the HW to be aware of its virtual Stream ID so it can replace with it= s > > > physical Stream ID. > > > > I imagine using this as well for the ATC invalidation commands. It > > would be very easy and simplifying if the command fixup just extracted > > the vSID from the ATC invalidation and used an xarray to turn it into > > a pSID and then pushed the resulting command. >=20 > You mean the nested SMMU series right? Actually the set_dev_id > ioctl was a part of that until we wanted to try DEV_INVALIDATE. >=20 > So again, yes, it makes sense to me that we move viommu and the > set_dev_id to the nested series, and then drop DEV_INVALIDATE. >=20 I'm right about to ask how the nesting series is going. Per earlier discussion iirc the nesting series will go in before VCMDQ?