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AJvYcCXzGGJ2/F3QnIPGeCmi9SBNpD3sNjgU5pP9s0949uqFz4donDWhkP7S/EnZgvJZL8FCJv56KwC6aiOoxK9CZnhOg5X0YKhIDa5CVcXBEdWT2HbXh1ooJOpp/uNc1oXf/s8+B4/JgSxrcA== X-Gm-Message-State: AOJu0Yz2Dt1uT4GFhfuRBY3veo5DZ7vuI/EDlO4aD1jOrW7HUpj4T9GS xUxiMWGMigFpoeUSHZOmaYeIKemhz0MnZcJhKnb+LSUfBXAwHHcy X-Received: by 2002:a17:902:dad1:b0:1f3:4945:28af with SMTP id d9443c01a7336-1f349452ae3mr13316705ad.11.1716479281862; Thu, 23 May 2024 08:48:01 -0700 (PDT) Received: from localhost.localdomain ([223.178.81.93]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-1f3361a6678sm18321085ad.178.2024.05.23.08.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 May 2024 08:48:01 -0700 (PDT) From: Kanak Shilledar X-Google-Original-From: Kanak Shilledar To: Cc: Kanak Shilledar , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Samuel Holland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [RESEND v3 0/2] dt-bindings: interrupt-controller: riscv,cpu-intc Date: Thu, 23 May 2024 21:17:46 +0530 Message-Id: <20240523154748.22670-1-kanakshilledar111@protonmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series of patches converts the RISC-V CPU interrupt controller to the newer dt-schema binding. Patch 1: This patch is currently at v3 as it has been previously rolled out. Contains the bindings for the interrupt controller. Patch 2: This patch is currently at v3. Contains the reference to the above interrupt controller. Thus, making all the RISC-V interrupt controller bindings in a centralized place. These patches are interdependent. Kanak Shilledar (2): dt-bindings: interrupt-controller: riscv,cpu-intc: convert to dtschema dt-bindings: riscv: cpus: add ref to interrupt-controller .../interrupt-controller/riscv,cpu-intc.txt | 52 ------------- .../interrupt-controller/riscv,cpu-intc.yaml | 73 +++++++++++++++++++ .../devicetree/bindings/riscv/cpus.yaml | 21 +----- 3 files changed, 74 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.yaml base-commit: 20cb38a7af88dc40095da7c2c9094da3873fea23 -- 2.34.1