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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF00004680.mail.protection.outlook.com (10.167.243.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7611.14 via Frontend Transport; Thu, 23 May 2024 15:56:56 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 23 May 2024 10:56:55 -0500 From: Yazen Ghannam To: CC: , , , , , Yazen Ghannam Subject: [PATCH 0/9] AMD MCA interrupts rework Date: Thu, 23 May 2024 10:56:32 -0500 Message-ID: <20240523155641.2805411-1-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00004680:EE_|SJ0PR12MB7008:EE_ X-MS-Office365-Filtering-Correlation-Id: 96a12158-3abb-4192-13c6-08dc7b40f8df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|1800799015|376005|36860700004; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:56:56.2791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96a12158-3abb-4192-13c6-08dc7b40f8df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7008 Hi all, This set unifies the AMD MCA interrupt handlers with common MCA code. The goal is to avoid duplicating functionality like reading and clearing MCA banks. Patches 1-3 are minor changes for issues found during testing. Patches 4-9 are revised work of patches 6-12 from the following set: https://lkml.kernel.org/r/20240404151359.47970-1-yazen.ghannam@amd.com In addition to addressing review comments, I tried to reduce the amount of refactoring to only what is functionally needed for fixes and features. I still want to do a broader clean up, but I think that can come later. Patch 7 has a minor merge conflict with the following set: https://lkml.kernel.org/r/20240521125434.1555845-1-yazen.ghannam@amd.com The sets do not depend on each other, so I thought to keep them separate. But I can rebase this one on the other, if needed. Thanks, Yazen Yazen Ghannam (9): x86/mce/inject: Only write MCA_MISC with user-set value x86/mce: Remove unused variable and return value in machine_check_poll() x86/mce: Increment MCP count only for timer calls x86/mce: Move machine_check_poll() status checks to helper functions x86/mce: Skip AMD threshold init if no threshold banks found x86/mce: Unify AMD THR handler with MCA Polling x86/mce: Unify AMD DFR handler with MCA Polling x86/mce/amd: Enable interrupt vectors once per-CPU on SMCA systems x86/mce/amd: Support SMCA Corrected Error Interrupt arch/x86/include/asm/mce.h | 3 +- arch/x86/kernel/cpu/mce/amd.c | 274 +++++++++-------------------- arch/x86/kernel/cpu/mce/core.c | 143 +++++++++------ arch/x86/kernel/cpu/mce/inject.c | 8 +- arch/x86/kernel/cpu/mce/internal.h | 7 +- 5 files changed, 186 insertions(+), 249 deletions(-) base-commit: 108c6494bdf1dfeaefc0a506e2f471aa92fafdd6 -- 2.34.1