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b=MSu3ybZTg8BMjTHiMSL7eit6fDs7/LYW1i0G7KLFbM2EeumOWXqT2XpXPASstv5At 5jdP7kVkf/q9/6ljobGWGw5tzKtwfkemmMMMnJ9g5oluCZN1hEyfwGSqbOcI/f6Q0i KWcqyWkHwiTDi7aex6KKy8CuxXOPFVUjrj8Ng4AE= Received: by gentwo.org (Postfix, from userid 1003) id 3A77340251; Thu, 23 May 2024 11:09:11 -0700 (PDT) Received: from localhost (localhost [127.0.0.1]) by gentwo.org (Postfix) with ESMTP id 39BF5401F3; Thu, 23 May 2024 11:09:11 -0700 (PDT) Date: Thu, 23 May 2024 11:09:11 -0700 (PDT) From: "Christoph Lameter (Ampere)" To: Catalin Marinas cc: Yang Shi , will@kernel.org, anshuman.khandual@arm.com, scott@os.amperecomputing.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [v2 PATCH] arm64: mm: force write fault for atomic RMW instructions In-Reply-To: Message-ID: <640f8606-2757-4e82-721f-9625d48ded65@gentwo.org> References: <20240520165636.802268-1-yang@os.amperecomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed On Thu, 23 May 2024, Catalin Marinas wrote: > On Mon, May 20, 2024 at 09:56:36AM -0700, Yang Shi wrote: >> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h >> index db1aeacd4cd9..1cc73664fc55 100644 >> --- a/arch/arm64/include/asm/insn.h >> +++ b/arch/arm64/include/asm/insn.h >> @@ -319,6 +319,7 @@ static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ >> * "-" means "don't care" >> */ >> __AARCH64_INSN_FUNCS(class_branch_sys, 0x1c000000, 0x14000000) >> +__AARCH64_INSN_FUNCS(class_atomic, 0x3b200c00, 0x38200000) > > While this class includes all atomics that currently require write > permission, there's some unallocated space in this range and we don't > know what future architecture versions may introduce. Unfortunately we > need to check each individual atomic op in this class (not sure what the > overhead will be). Can you tell us which bits or pattern is not allocated? Maybe we can exclude that from the pattern.