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Date: Thu, 23 May 2024 19:06:04 +0000
To: Emil Renner Berthing <kernel@esmil.dk>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
From: H Bell <dmoo_dv@protonmail.com>
Subject: [PATCH] RISC-V: add Star64 board devicetree
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The Pine64 Star64 is a development board based on the Starfive JH7110 SoC.
The board features:

- JH7110 SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x eMMC slot
- 1x MicroSD slot
- 1x QSPI Flash
- 2x 1Gbps Ethernet port
- 1x HDMI port
- 1x 4-lane DSI
- 1x 2-lane CSI
- 1x PCIe 2.0 x1 lane

Signed-off-by: Henry Bell <dmoo_dv@protonmail.com>
Cc: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/boot/dts/starfive/Makefile         |  1 +
 .../dts/starfive/jh7110-pine64-star64.dts     | 62 +++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/st=
arfive/Makefile
index 2fa0cd7f31c3..7a163a7d6ba3 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -9,5 +9,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7100-beaglev-starlight.d=
tb
 dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7100-starfive-visionfive-v1.dtb
=20
 dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-milkv-mars.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-pine64-star64.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.3b.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/r=
iscv/boot/dts/starfive/jh7110-pine64-star64.dts
new file mode 100644
index 000000000000..c70fffd51181
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+* Copyright (C) 2022 StarFive Technology Co., Ltd.
+* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+*/
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+=09model =3D "Pine64 Star64";
+=09compatible =3D "pine64,star64", "starfive,jh7110";
+=09=09aliases {
+=09=09=09=09ethernet1 =3D &gmac1;
+=09=09};
+};
+
+&gmac0 {
+=09starfive,tx-use-rgmii-clk;
+=09assigned-clocks =3D <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+=09assigned-clock-parents =3D <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+};
+
+&gmac1 {
+=09phy-handle =3D <&phy1>;
+=09phy-mode =3D "rgmii-id";
+=09status =3D "okay";
+=09starfive,tx-use-rgmii-clk;
+=09assigned-clocks =3D <&syscrg JH7110_SYSCLK_GMAC1_TX>;
+=09assigned-clock-parents =3D <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
+
+=09mdio {
+=09=09#address-cells =3D <1>;
+=09=09#size-cells =3D <0>;
+=09=09compatible =3D "snps,dwmac-mdio";
+
+=09=09phy1: ethernet-phy@1 {
+=09=09=09reg =3D <0>;
+=09=09};
+=09};
+};
+
+&phy0 {
+=09motorcomm,tx-clk-adj-enabled;
+=09motorcomm,tx-clk-10-inverted;
+=09motorcomm,tx-clk-100-inverted;
+=09motorcomm,tx-clk-1000-inverted;
+=09motorcomm,rx-clk-drv-microamp =3D <2910>;
+=09motorcomm,rx-data-drv-microamp =3D <2910>;
+=09rx-internal-delay-ps =3D <1900>;=20
+=09tx-internal-delay-ps =3D <1500>;
+};
+
+&phy1 {
+=09motorcomm,tx-clk-adj-enabled;
+=09motorcomm,tx-clk-10-inverted;
+=09motorcomm,tx-clk-100-inverted;
+=09motorcomm,rx-clk-drv-microamp =3D <2910>;
+=09motorcomm,rx-data-drv-microamp =3D <2910>;
+=09rx-internal-delay-ps =3D <0>;
+=09tx-internal-delay-ps =3D <300>;
+};
--=20
2.44.0