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Message-ID: <tencent_1E3506F09D08066B8F3BAEE136C4F887540A@qq.com>
From: Yangyu Chen <cyy@cyyself.name>
To: linux-riscv@lists.infradead.org
Cc: Elliott Hughes <enh@google.com>,
	Charlie Jenkins <charlie@rivosinc.com>,
	Jonathan Corbet <corbet@lwn.net>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Evan Green <evan@rivosinc.com>,
	=?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= <cleger@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	linux-kernel@vger.kernel.org,
	linux-doc@vger.kernel.org,
	Yangyu Chen <cyy@cyyself.name>
Subject: [PATCH v2 0/3] docs: riscv: Some clarifies on hwprobe misaligned performance
Date: Fri, 24 May 2024 11:34:50 +0800
Precedence: bulk
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This patchset clarifies some unclear things about hwprobe's misaligned
performance. Including:

- hwprobe misaligned performance is only applied to scalar from patch [1]
- The defined keys of RISCV_HWPROBE_MISALIGNED_* are values not bitmasks

I cherry-picked [1] rather than write dependency because the original patch
was submitted with lines wrapped to 80 characters. We can't directly apply
that patch using `git am` .

Changes in v2:
- Add fixes to the code in arch/riscv/and include/asm/hwprobe.h

v1: https://lore.kernel.org/linux-riscv/tencent_9D721BDDF88C04DBB5151D57711D62524209@qq.com/

[1] https://lore.kernel.org/linux-riscv/CAJgzZorn5anPH8dVPqvjVWmLKqTi5bkLDR=FH-ZAcdXFnNe8Eg@mail.gmail.com/

Yangyu Chen (2):
  docs: riscv: hwprobe: Clarify misaligned keys are values not bitmasks
  RISC-V: hwprobe: not treat KEY_CPUPERF_0 as bitmask

enh (1):
  docs: riscv: Clarify risc-v hwprobe RISCV_HWPROBE_MISALIGNED_* docs.

 Documentation/arch/riscv/hwprobe.rst | 31 ++++++++++++++++------------
 arch/riscv/include/asm/hwprobe.h     |  1 -
 2 files changed, 18 insertions(+), 14 deletions(-)

-- 
2.45.1