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From: Xiao Wang <xiao.w.wang@intel.com>
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	Xiao Wang <xiao.w.wang@intel.com>
Subject: [PATCH bpf-next v4 0/2] riscv, bpf: Introduce Zba optimization
Date: Fri, 24 May 2024 15:55:41 +0800
Message-Id: <20240524075543.4050464-1-xiao.w.wang@intel.com>
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The riscv Zba extension provides instructions to accelerate the generation
of addresses that index into arrays of basic data types, bpf JIT generated
insn counts could be reduced by leveraging Zba for address calculation.

The first patch introduces RISCV_ISA_ZBA Kconfig option and uses Zba add.uw
insn to optimize zextw operation.

The second patch uses Zba shift-and-add insns to optimize address
calculation for array of unsigned long data.

Thanks,
Xiao

v4:
* Combine the second patch (previously v1) and the first patch into a series. (Bjorn)
* Rebase the second patch on bpf-next tree.
* Link to v3: https://lore.kernel.org/bpf/20240516090430.493122-1-xiao.w.wang@intel.com/

v3:
* Remove the Kconfig dependencies on TOOLCHAIN_HAS_ZBA and
  RISCV_ALTERNATIVE. (Andrew)
* Link to v2: https://lore.kernel.org/bpf/20240511023436.3282285-1-xiao.w.wang@intel.com/

v2:
* Add Zba description in the Kconfig. (Lehui)
* Reword the Kconfig help message to make it clearer. (Conor)
* Link to v1: https://lore.kernel.org/bpf/20240507104528.435980-1-xiao.w.wang@intel.com/

Xiao Wang (2):
  riscv, bpf: Optimize zextw insn with Zba extension
  riscv, bpf: Introduce shift add helper with Zba optimization

 arch/riscv/Kconfig              | 12 ++++++++
 arch/riscv/net/bpf_jit.h        | 51 +++++++++++++++++++++++++++++++++
 arch/riscv/net/bpf_jit_comp32.c |  3 +-
 arch/riscv/net/bpf_jit_comp64.c |  9 ++----
 4 files changed, 67 insertions(+), 8 deletions(-)


base-commit: 5c1672705a1a2389f5ad78e0fea6f08ed32d6f18
-- 
2.25.1