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Date: Fri, 24 May 2024 10:16:39 +0200
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To: Sean Anderson <sean.anderson@linux.dev>,
 linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
 kernel-janitors@vger.kernel.org, =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?=
 <kw@linux.com>, Lorenzo Pieralisi <lpieralisi@kernel.org>,
 Rob Herring <robh@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
 Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
 Bjorn Helgaas <bhelgaas@google.com>,
 Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
 Michal Simek <michal.simek@amd.com>, Michal Simek <michal.simek@xilinx.com>,
 Thippeswamy Havalige <thippeswamy.havalige@amd.com>
References: <20240520145402.2526481-7-sean.anderson@linux.dev>
Subject: Re: [PATCH v3 6/7] PCI: xilinx-nwl: Add phy support
Content-Language: en-GB
From: Markus Elfring <Markus.Elfring@web.de>
In-Reply-To: <20240520145402.2526481-7-sean.anderson@linux.dev>
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> Add support for enabling/disabling PCIe phys. We can't really do
> anything about failures in the disable/remove path, so just warn.
=E2=80=A6
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
=E2=80=A6
> @@ -818,12 +876,15 @@ static int nwl_pcie_probe(struct platform_device *=
pdev)
>  		err =3D nwl_pcie_enable_msi(pcie);
>  		if (err < 0) {
>  			dev_err(dev, "failed to enable MSI support: %d\n", err);
> -			goto err_clk;
> +			goto err_phy;
>  		}
>  	}
>
>  	err =3D pci_host_probe(bridge);
>
> +err_phy:
> +	if (err)
> +		nwl_pcie_phy_disable(pcie);
>  err_clk:
>  	if (err)
>  		clk_disable_unprepare(pcie->clk);

I got the impression that some source code adjustments should be performed
in another separate update step for this function implementation.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Do=
cumentation/process/submitting-patches.rst?h=3Dv6.9#n81

You propose to extend the exception handling here.
Does such information indicate a need for another tag =E2=80=9CFixes=E2=80=
=9D?

How do you think about to increase the usage of a corresponding goto chain=
?
https://wiki.sei.cmu.edu/confluence/display/c/MEM12-C.+Consider+using+a+go=
to+chain+when+leaving+a+function+on+error+when+using+and+releasing+resourc=
es

Would you become more interested in the application of scope-based resourc=
e management?

Regards,
Markus