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From: Prabhakar <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Magnus Damm <magnus.damm@gmail.com>
Cc: linux-renesas-soc@vger.kernel.org,
	linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions
Date: Fri, 24 May 2024 09:27:58 +0100
Message-Id: <20240524082800.333991-3-prabhakar.mahadev-lad.rj@bp.renesas.com>
In-Reply-To: <20240524082800.333991-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
References: <20240524082800.333991-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Precedence: bulk
MIME-Version: 1.0
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From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
(CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
Hardware User's Manual (Rev.1.01, Feb. 2024).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 include/dt-bindings/clock/r9a09g057-cpg.h | 644 ++++++++++++++++++++++
 1 file changed, 644 insertions(+)
 create mode 100644 include/dt-bindings/clock/r9a09g057-cpg.h

diff --git a/include/dt-bindings/clock/r9a09g057-cpg.h b/include/dt-bindings/clock/r9a09g057-cpg.h
new file mode 100644
index 000000000000..01b9eadcf031
--- /dev/null
+++ b/include/dt-bindings/clock/r9a09g057-cpg.h
@@ -0,0 +1,644 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Clock list */
+#define R9A09G057_SYS_0_PCLK				0
+#define R9A09G057_DMAC_0_ACLK				1
+#define R9A09G057_DMAC_1_ACLK				2
+#define R9A09G057_DMAC_2_ACLK				3
+#define R9A09G057_DMAC_3_ACLK				4
+#define R9A09G057_DMAC_4_ACLK				5
+#define R9A09G057_ICU_0_PCLK_I				6
+#define R9A09G057_CRC_0_CLK_CRC				7
+#define R9A09G057_CA55_0_CORE_CLK0			8
+#define R9A09G057_CA55_0_CORE_CLK1			9
+#define R9A09G057_CA55_0_CORE_CLK2			10
+#define R9A09G057_CA55_0_CORE_CLK3			11
+#define R9A09G057_CA55_0_SCLK				12
+#define R9A09G057_CA55_0_PCLK				13
+#define R9A09G057_CA55_0_ATCLK				14
+#define R9A09G057_CA55_0_GICCLK				15
+#define R9A09G057_CA55_0_PERIPHCLK			16
+#define R9A09G057_CA55_0_ACLK				17
+#define R9A09G057_CA55_0_TSCLK				18
+#define R9A09G057_CR8_0_CLK				19
+#define R9A09G057_CR8_0_PERIPHCLK			20
+#define R9A09G057_CR8_0_ACLK				21
+#define R9A09G057_CR8_0_ATCLK0				22
+#define R9A09G057_CR8_0_TSCLK				23
+#define R9A09G057_CR8_0_DBGCLK				24
+#define R9A09G057_CM33_CLK0				25
+#define R9A09G057_CM33_CLK1				26
+#define R9A09G057_GIC_0_GICCLK				27
+#define R9A09G057_SRAM_0_ACLK				28
+#define R9A09G057_SRAM_1_ACLK				29
+#define R9A09G057_SRAM_2_ACLK				30
+#define R9A09G057_SRAM_3_ACLK				31
+#define R9A09G057_SRAM_4_ACLK				32
+#define R9A09G057_SRAM_5_ACLK				33
+#define R9A09G057_SRAM_6_ACLK				34
+#define R9A09G057_SRAM_7_ACLK				35
+#define R9A09G057_SRAM_8_ACLK				36
+#define R9A09G057_SRAM_9_ACLK				37
+#define R9A09G057_SRAM_10_ACLK				38
+#define R9A09G057_SRAM_11_ACLK				39
+#define R9A09G057_BTROM_0_ACLK				40
+#define R9A09G057_CST_0_CS_CLK				41
+#define R9A09G057_CST_0_TS_CLK				42
+#define R9A09G057_CST_0_APB_SB_CLK			43
+#define R9A09G057_CST_0_APB_CA55_CLK			44
+#define R9A09G057_CST_0_APB_CR8_CLK			45
+#define R9A09G057_CST_0_APB_CM33_CLK			46
+#define R9A09G057_CST_0_AHB_CM33_CLK			47
+#define R9A09G057_CST_0_AHB_ATH_CLK			48
+#define R9A09G057_CST_0_ATB_CA55_CLK			49
+#define R9A09G057_CST_0_ATB_CR8_CLK			50
+#define R9A09G057_CST_0_ATB_CM33_CLK			51
+#define R9A09G057_CST_0_ATB_CST_CLK			52
+#define R9A09G057_CST_0_SWCLKTCK			53
+#define R9A09G057_CST_0_AXI_ETR_CLK			54
+#define R9A09G057_CST_0_AXI_SB_CLK			55
+#define R9A09G057_SYC_0_CNT_CLK				56
+#define R9A09G057_MHU_0_PCLK				57
+#define R9A09G057_GPT_0_PCLK_SFR			58
+#define R9A09G057_GPT_0_CLKS_GPT			59
+#define R9A09G057_GPT_1_PCLK_SFR			60
+#define R9A09G057_GPT_1_CLKS_GPT			61
+#define R9A09G057_POEGA_0_PCLK				62
+#define R9A09G057_POEGB_0_PCLK				63
+#define R9A09G057_POEGC_0_PCLK				64
+#define R9A09G057_POEGD_0_PCLK				65
+#define R9A09G057_POEGA_1_PCLK				66
+#define R9A09G057_POEGB_1_PCLK				67
+#define R9A09G057_POEGC_1_PCLK				68
+#define R9A09G057_POEGD_1_PCLK				69
+#define R9A09G057_CMTW_0_CLKM				70
+#define R9A09G057_CMTW_1_CLKM				71
+#define R9A09G057_CMTW_2_CLKM				72
+#define R9A09G057_CMTW_3_CLKM				73
+#define R9A09G057_CMTW_4_CLKM				74
+#define R9A09G057_CMTW_5_CLKM				75
+#define R9A09G057_CMTW_6_CLKM				76
+#define R9A09G057_CMTW_7_CLKM				77
+#define R9A09G057_GTM_0_PCLK				78
+#define R9A09G057_GTM_1_PCLK				79
+#define R9A09G057_GTM_2_PCLK				80
+#define R9A09G057_GTM_3_PCLK				81
+#define R9A09G057_GTM_4_PCLK				82
+#define R9A09G057_GTM_5_PCLK				83
+#define R9A09G057_GTM_6_PCLK				84
+#define R9A09G057_GTM_7_PCLK				85
+#define R9A09G057_WDT_0_CLKP				86
+#define R9A09G057_WDT_0_CLK_LOCO			87
+#define R9A09G057_WDT_1_CLKP				88
+#define R9A09G057_WDT_1_CLK_LOCO			89
+#define R9A09G057_WDT_2_CLKP				90
+#define R9A09G057_WDT_2_CLK_LOCO			91
+#define R9A09G057_WDT_3_CLKP				92
+#define R9A09G057_WDT_3_CLK_LOCO			93
+#define R9A09G057_RTC_0_CLK_RTC				94
+#define R9A09G057_RSPI_0_PCLK				95
+#define R9A09G057_RSPI_0_PCLK_SFR			96
+#define R9A09G057_RSPI_0_TCLK				97
+#define R9A09G057_RSPI_1_PCLK				98
+#define R9A09G057_RSPI_1_PCLK_SFR			99
+#define R9A09G057_RSPI_1_TCLK				100
+#define R9A09G057_RSPI_2_PCLK				101
+#define R9A09G057_RSPI_2_PCLK_SFR			102
+#define R9A09G057_RSPI_2_TCLK				103
+#define R9A09G057_RSCI_0_PCLK				104
+#define R9A09G057_RSCI_0_PCLK_SFR			105
+#define R9A09G057_RSCI_0_TCLK				106
+#define R9A09G057_RSCI_0_PS_PS3_N			107
+#define R9A09G057_RSCI_0_PS_PS2_N			108
+#define R9A09G057_RSCI_0_PS_PS1_N			109
+#define R9A09G057_RSCI_1_PCLK				110
+#define R9A09G057_RSCI_1_PCLK_SFR			111
+#define R9A09G057_RSCI_1_TCLK				112
+#define R9A09G057_RSCI_1_PS_PS3_N			113
+#define R9A09G057_RSCI_1_PS_PS2_N			114
+#define R9A09G057_RSCI_1_PS_PS1_N			115
+#define R9A09G057_RSCI_2_PCLK				116
+#define R9A09G057_RSCI_2_PCLK_SFR			117
+#define R9A09G057_RSCI_2_TCLK				118
+#define R9A09G057_RSCI_2_PS_PS3_N			119
+#define R9A09G057_RSCI_2_PS_PS2_N			120
+#define R9A09G057_RSCI_2_PS_PS1_N			121
+#define R9A09G057_RSCI_3_PCLK				122
+#define R9A09G057_RSCI_3_PCLK_SFR			123
+#define R9A09G057_RSCI_3_TCLK				124
+#define R9A09G057_RSCI_3_PS_PS3_N			125
+#define R9A09G057_RSCI_3_PS_PS2_N			126
+#define R9A09G057_RSCI_3_PS_PS1_N			127
+#define R9A09G057_RSCI_4_PCLK				128
+#define R9A09G057_RSCI_4_PCLK_SFR			129
+#define R9A09G057_RSCI_4_TCLK				130
+#define R9A09G057_RSCI_4_PS_PS3_N			131
+#define R9A09G057_RSCI_4_PS_PS2_N			132
+#define R9A09G057_RSCI_4_PS_PS1_N			133
+#define R9A09G057_RSCI_5_PCLK				134
+#define R9A09G057_RSCI_5_PCLK_SFR			135
+#define R9A09G057_RSCI_5_TCLK				136
+#define R9A09G057_RSCI_5_PS_PS3_N			137
+#define R9A09G057_RSCI_5_PS_PS2_N			138
+#define R9A09G057_RSCI_5_PS_PS1_N			139
+#define R9A09G057_RSCI_6_PCLK				140
+#define R9A09G057_RSCI_6_PCLK_SFR			141
+#define R9A09G057_RSCI_6_TCLK				142
+#define R9A09G057_RSCI_6_PS_PS3_N			143
+#define R9A09G057_RSCI_6_PS_PS2_N			144
+#define R9A09G057_RSCI_6_PS_PS1_N			145
+#define R9A09G057_RSCI_7_PCLK				146
+#define R9A09G057_RSCI_7_PCLK_SFR			147
+#define R9A09G057_RSCI_7_TCLK				148
+#define R9A09G057_RSCI_7_PS_PS3_N			149
+#define R9A09G057_RSCI_7_PS_PS2_N			150
+#define R9A09G057_RSCI_7_PS_PS1_N			151
+#define R9A09G057_RSCI_8_PCLK				152
+#define R9A09G057_RSCI_8_PCLK_SFR			153
+#define R9A09G057_RSCI_8_TCLK				154
+#define R9A09G057_RSCI_8_PS_PS3_N			155
+#define R9A09G057_RSCI_8_PS_PS2_N			156
+#define R9A09G057_RSCI_8_PS_PS1_N			157
+#define R9A09G057_RSCI_9_PCLK				158
+#define R9A09G057_RSCI_9_PCLK_SFR			159
+#define R9A09G057_RSCI_9_TCLK				160
+#define R9A09G057_RSCI_9_PS_PS3_N			161
+#define R9A09G057_RSCI_9_PS_PS2_N			162
+#define R9A09G057_RSCI_9_PS_PS1_N			163
+#define R9A09G057_SCIF_0_CLK_PCK			164
+#define R9A09G057_I3C_0_PCLKRW				165
+#define R9A09G057_I3C_0_PCLK				166
+#define R9A09G057_I3C_0_TCLK				167
+#define R9A09G057_RIIC_8_CKM				168
+#define R9A09G057_RIIC_0_CKM				169
+#define R9A09G057_RIIC_1_CKM				170
+#define R9A09G057_RIIC_2_CKM				171
+#define R9A09G057_RIIC_3_CKM				172
+#define R9A09G057_RIIC_4_CKM				173
+#define R9A09G057_RIIC_5_CKM				174
+#define R9A09G057_RIIC_6_CKM				175
+#define R9A09G057_RIIC_7_CKM				176
+#define R9A09G057_CANFD_0_PCLK				177
+#define R9A09G057_CANFD_0_CLK_RAM			178
+#define R9A09G057_CANFD_0_CLKC				179
+#define R9A09G057_SPI_HCLK				180
+#define R9A09G057_SPI_ACLK				181
+#define R9A09G057_SPI_CLK_SPI				182
+#define R9A09G057_SPI_CLK_SPIX2				183
+#define R9A09G057_IOTOP_0_SHCLK				184
+#define R9A09G057_SDHI_0_IMCLK				185
+#define R9A09G057_SDHI_0_IMCLK2				186
+#define R9A09G057_SDHI_0_CLK_HS				187
+#define R9A09G057_SDHI_0_ACLK				188
+#define R9A09G057_SDHI_1_IMCLK				189
+#define R9A09G057_SDHI_1_IMCLK2				190
+#define R9A09G057_SDHI_1_CLK_HS				191
+#define R9A09G057_SDHI_1_ACLK				192
+#define R9A09G057_SDHI_2_IMCLK				193
+#define R9A09G057_SDHI_2_IMCLK2				194
+#define R9A09G057_SDHI_2_CLK_HS				195
+#define R9A09G057_SDHI_2_ACLK				196
+#define R9A09G057_USB30_CLK_RESERVED0			197
+#define R9A09G057_USB30_CLK_RESERVED1			198
+#define R9A09G057_USB30_CLK_RESERVED2			199
+#define R9A09G057_USB30_CLK_RESERVED3			200
+#define R9A09G057_USB31_CLK_RESERVED0			201
+#define R9A09G057_USB31_CLK_RESERVED1			202
+#define R9A09G057_USB31_CLK_RESERVED2			203
+#define R9A09G057_USB31_CLK_RESERVED3			204
+#define R9A09G057_USB20_CLK_RESERVED0			205
+#define R9A09G057_USB21_CLK_RESERVED0			206
+#define R9A09G057_USB20_USB21_CLK_RESERVED0		207
+#define R9A09G057_USB20_CLK_RESERVED1			208
+#define R9A09G057_USB21_CLK_RESERVED1			209
+#define R9A09G057_USB20_CLK_RESERVED2			210
+#define R9A09G057_USB21_CLK_RESERVED2			211
+#define R9A09G057_GBETH0_CLK_RESERVED0			212
+#define R9A09G057_GBETH0_CLK_RESERVED1			213
+#define R9A09G057_GBETH0_CLK_RESERVED2			214
+#define R9A09G057_GBETH0_CLK_RESERVED3			215
+#define R9A09G057_GBETH0_CLK_RESERVED4			216
+#define R9A09G057_GBETH0_CLK_RESERVED5			217
+#define R9A09G057_GBETH0_CLK_RESERVED6			218
+#define R9A09G057_GBETH1_CLK_RESERVED0			219
+#define R9A09G057_GBETH1_CLK_RESERVED1			220
+#define R9A09G057_GBETH1_CLK_RESERVED2			221
+#define R9A09G057_GBETH1_CLK_RESERVED3			222
+#define R9A09G057_GBETH1_CLK_RESERVED4			223
+#define R9A09G057_GBETH1_CLK_RESERVED5			224
+#define R9A09G057_GBETH1_CLK_RESERVED6			225
+#define R9A09G057_PCIE_0_ACLK				226
+#define R9A09G057_PCIE_0_CLK_PMU			227
+#define R9A09G057_DDR0_CLK_RESERVED0			228
+#define R9A09G057_DDR0_CLK_RESERVED1			229
+#define R9A09G057_DDR0_CLK_RESERVED2			230
+#define R9A09G057_DDR0_CLK_RESERVED3			231
+#define R9A09G057_DDR0_CLK_RESERVED4			232
+#define R9A09G057_DDR0_CLK_RESERVED5			233
+#define R9A09G057_DDR0_CLK_RESERVED6			234
+#define R9A09G057_DDR1_CLK_RESERVED0			235
+#define R9A09G057_DDR1_CLK_RESERVED1			236
+#define R9A09G057_DDR1_CLK_RESERVED2			237
+#define R9A09G057_DDR1_CLK_RESERVED3			238
+#define R9A09G057_DDR1_CLK_RESERVED4			239
+#define R9A09G057_DDR1_CLK_RESERVED5			240
+#define R9A09G057_DDR1_CLK_RESERVED6			241
+#define R9A09G057_CRU_0_ACLK				242
+#define R9A09G057_CRU_0_VCLK				243
+#define R9A09G057_CRU_0_PCLK				244
+#define R9A09G057_CRU_1_ACLK				245
+#define R9A09G057_CRU_1_VCLK				246
+#define R9A09G057_CRU_1_PCLK				247
+#define R9A09G057_CRU_2_ACLK				248
+#define R9A09G057_CRU_2_VCLK				249
+#define R9A09G057_CRU_2_PCLK				250
+#define R9A09G057_CRU_3_ACLK				251
+#define R9A09G057_CRU_3_VCLK				252
+#define R9A09G057_CRU_3_PCLK				253
+#define R9A09G057_ISP_CLK_RESERVED0			254
+#define R9A09G057_ISP_CLK_RESERVED1			255
+#define R9A09G057_ISP_CLK_RESERVED2			256
+#define R9A09G057_ISP_CLK_RESERVED3			257
+#define R9A09G057_ISU_0_ACLK				258
+#define R9A09G057_ISU_0_PCLK				259
+#define R9A09G057_DSI_0_PCLK				260
+#define R9A09G057_DSI_0_ACLK				261
+#define R9A09G057_DSI_0_VCLK1				262
+#define R9A09G057_DSI_0_LPCLK				263
+#define R9A09G057_DSI_0_PLLREFCLK			264
+#define R9A09G057_LCDC_0_CLK_A				265
+#define R9A09G057_LCDC_0_CLK_P				266
+#define R9A09G057_LCDC_0_CLK_D				267
+#define R9A09G057_GPU_0_CLK				268
+#define R9A09G057_GPU_0_AXI_CLK				269
+#define R9A09G057_GPU_0_ACE_CLK				270
+#define R9A09G057_VCD_0_ACLK				271
+#define R9A09G057_VCD_0_PCLK				272
+#define R9A09G057_SSIF_0_CLK				273
+#define R9A09G057_SCU_0_CLK				274
+#define R9A09G057_SCU_0_CLKX2				275
+#define R9A09G057_DMACPP_0_CLK				276
+#define R9A09G057_ADG_0_CLKS1				277
+#define R9A09G057_ADG_0_CLK_195M			278
+#define R9A09G057_ADG_0_AUDIO_CLKA			279
+#define R9A09G057_ADG_0_AUDIO_CLKB			280
+#define R9A09G057_ADG_0_AUDIO_CLKC			281
+#define R9A09G057_SPDIF_0_CLKP				282
+#define R9A09G057_SPDIF_1_CLKP				283
+#define R9A09G057_SPDIF_2_CLKP				284
+#define R9A09G057_PDM_0_PCLK				285
+#define R9A09G057_PDM_0_PCLK_SFR			286
+#define R9A09G057_PDM_0_CCLK				287
+#define R9A09G057_PDM_1_PCLK				288
+#define R9A09G057_PDM_1_PCLK_SFR			289
+#define R9A09G057_PDM_1_CCLK				290
+#define R9A09G057_ADC_0_PCLK				291
+#define R9A09G057_ADC_0_ADCLK				292
+#define R9A09G057_TSU_0_PCLK				293
+#define R9A09G057_TSU_1_PCLK				294
+#define R9A09G057_OTPC_0_CLKP1D				295
+#define R9A09G057_OTPC_0_PCLK				296
+#define R9A09G057_OTPC_0_SCLK				297
+#define R9A09G057_DRP_0_DCLKIN				298
+#define R9A09G057_DRP_0_ACLK				299
+#define R9A09G057_DRP_0_INITCLK				300
+#define R9A09G057_DRPAI_0_DCLKIN			301
+#define R9A09G057_DRPAI_0_ACLK				302
+#define R9A09G057_DRPAI_0_INITCLK			303
+#define R9A09G057_DRPAI_0_MCLK				304
+#define R9A09G057_RCPU_AXI_CLK200DG_RCP			305
+#define R9A09G057_RCPU_AXI_CLK400DG_ACP			306
+#define R9A09G057_RCPU_AXI_CLK200CF			307
+#define R9A09G057_RCPU_AXI_CLK100CF			308
+#define R9A09G057_RCPU_AXI_CLK50CF			309
+#define R9A09G057_MCPU_AXI_CLK200CG_MCP			310
+#define R9A09G057_MCPU_AXI_CLK100CF_MCP			311
+#define R9A09G057_MCPU_AXI_CLK100CG_MCP			312
+#define R9A09G057_MCPU_AXI_CLK50CG_ADC			313
+#define R9A09G057_MCPU_AXI_CLK50CF_MCP			314
+#define R9A09G057_MCPU_AXI_CLK24			315
+#define R9A09G057_ACPU_AXI_CLK400DG_ACP			316
+#define R9A09G057_ACPU_AXI_CLK200DG_ACP			317
+#define R9A09G057_ACPU_AXI_CLK400DG_DRP			318
+#define R9A09G057_ACPU_AXI_CLK200CG_MCP			319
+#define R9A09G057_ACPU_AXI_CLK200DF			320
+#define R9A09G057_ACPU_AXI_CLK200CF			321
+#define R9A09G057_ACPU_AXI_CLK100DG_ACP			322
+#define R9A09G057_ACPU_AXI_CLK100DF			323
+#define R9A09G057_ACPU_AXI_CLK100CF			324
+#define R9A09G057_ACPU_AXI_CLK24			325
+#define R9A09G057_ACPU_PERI_DDR_AXI_CLK100DG_ACP	326
+#define R9A09G057_VIDEO0_AXI_CLK400DG_ACP		327
+#define R9A09G057_VIDEO0_AXI_CLK400DG_DRP		328
+#define R9A09G057_VIDEO0_AXI_CLK630DG_ISP		329
+#define R9A09G057_ACPU_PERI_VIDEO0_AXI_CLK400DG_ACP	330
+#define R9A09G057_ACPU_PERI_VIDEO0_AXI_CLK100DF		331
+#define R9A09G057_VIDEO1_AXI_CLK400DG_ACP		332
+#define R9A09G057_VIDEO1_AXI_CLK100DG_ACP		333
+#define R9A09G057_VIDEO1_AXI_CLK400DG_DRP		334
+#define R9A09G057_VIDEO1_AXI_CLK400DF			335
+#define R9A09G057_VIDEO1_AXI_CLK630DG_ISU		336
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_CLK100DG_ACP	337
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_CLK200DF		338
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_CLK100DF		339
+#define R9A09G057_DRP_AXI_CLK400DG_DRP			340
+#define R9A09G057_ACPU_PERI_DRP0_AXI_CLK400DG_DRP	341
+#define R9A09G057_ACPU_PERI_DRP1_AXI_CLK400DG_DRP	342
+#define R9A09G057_COM_AXI_CLK400DG_ACP			343
+#define R9A09G057_COM_AXI_CLK200DG_ACP			344
+#define R9A09G057_COM_AXI_CLK400DG_DRP			345
+#define R9A09G057_COM_AXI_CLK200DF			346
+#define R9A09G057_ACPU_PERI_COM0_AXI_CLK400DG_ACP	347
+#define R9A09G057_ACPU_PERI_COM0_AXI_CLK200DG_ACP	348
+#define R9A09G057_ACPU_PERI_COM0_AXI_CLK200DF		349
+#define R9A09G057_ACPU_PERI_COM1_AXI_CLK200DG_ACP	350
+#define R9A09G057_ACPU_PERI_COM1_AXI_CLK200DF		351
+#define R9A09G057_TZCDDR_0_CLK100DG_ACP_PCLK0		352
+#define R9A09G057_TZCDDR_0_CLK100DG_ACP_PCLK1		353
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK0		354
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK1		355
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK2		356
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK3		357
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK4		358
+#define R9A09G057_TZCDDR_1_CLK100DG_ACP_PCLK0		359
+#define R9A09G057_TZCDDR_1_CLK100DG_ACP_PCLK1		360
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK0		361
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK1		362
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK2		363
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK3		364
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK4		365
+
+/* Resets list */
+#define R9A09G057_SYS_0_PRESETN				0
+#define R9A09G057_DMAC_0_ARESETN			1
+#define R9A09G057_DMAC_1_ARESETN			2
+#define R9A09G057_DMAC_2_ARESETN			3
+#define R9A09G057_DMAC_3_ARESETN			4
+#define R9A09G057_DMAC_4_ARESETN			5
+#define R9A09G057_ICU_0_PRESETN_I			6
+#define R9A09G057_CRC_0_RST				7
+#define R9A09G057_CA55_RESET0				8
+#define R9A09G057_CA55_RESET1				9
+#define R9A09G057_CA55_RESET2				10
+#define R9A09G057_CA55_RESET3				11
+#define R9A09G057_CA55_RESET4				12
+#define R9A09G057_CA55_RESET5				13
+#define R9A09G057_CA55_RESET6				14
+#define R9A09G057_CA55_RESET7				15
+#define R9A09G057_CA55_RESET8				16
+#define R9A09G057_CA55_RESET9				17
+#define R9A09G057_CA55_RESET10				18
+#define R9A09G057_CA55_RESET11				19
+#define R9A09G057_CA55_RESET12				20
+#define R9A09G057_CA55_RESET13				21
+#define R9A09G057_CA55_RESET14				22
+#define R9A09G057_CA55_RESET15				23
+#define R9A09G057_CA55_RESET16				24
+#define R9A09G057_CR8_0_NCPURESET1			25
+#define R9A09G057_CR8_0_NCPURESET0			26
+#define R9A09G057_CR8_0_NPERIPHRESET			27
+#define R9A09G057_CR8_0_NSCURESET			28
+#define R9A09G057_CR8_0_NWDRESET1			29
+#define R9A09G057_CR8_0_NWDRESET0			30
+#define R9A09G057_CR8_0_NDBGRESET1			31
+#define R9A09G057_CR8_0_NDBGRESET0			32
+#define R9A09G057_CR8_0_NCTRESET			33
+#define R9A09G057_CR8_0_NETM0RESET			34
+#define R9A09G057_CR8_0_NETM1RESET			35
+#define R9A09G057_CR8_0_NTSRESET			36
+#define R9A09G057_CR8_0_NMISCRESET			37
+#define R9A09G057_CM33_RESET0				38
+#define R9A09G057_CM33_RESET1				39
+#define R9A09G057_CM33_RESET2				40
+#define R9A09G057_GIC_0_GICRESET_N			41
+#define R9A09G057_GIC_0_DBG_GICRESET_N			42
+#define R9A09G057_SRAM_0_ARESETN			43
+#define R9A09G057_SRAM_1_ARESETN			44
+#define R9A09G057_SRAM_2_ARESETN			45
+#define R9A09G057_SRAM_3_ARESETN			46
+#define R9A09G057_SRAM_4_ARESETN			47
+#define R9A09G057_SRAM_5_ARESETN			48
+#define R9A09G057_SRAM_6_ARESETN			49
+#define R9A09G057_SRAM_7_ARESETN			50
+#define R9A09G057_SRAM_8_ARESETN			51
+#define R9A09G057_SRAM_9_ARESETN			52
+#define R9A09G057_SRAM_10_ARESETN			53
+#define R9A09G057_SRAM_11_ARESETN			54
+#define R9A09G057_BTROM_0_ARESETN			55
+#define R9A09G057_CST_0_CS_RESETN			56
+#define R9A09G057_CST_0_TS_RESETN			57
+#define R9A09G057_CST_0_APB_SB_RESETN			58
+#define R9A09G057_CST_0_APB_CA55_RESETN			59
+#define R9A09G057_CST_0_APB_CM33_RESETN			60
+#define R9A09G057_CST_0_APB_CR8_RESETN			61
+#define R9A09G057_CST_0_AHB_CM33_RESETN			62
+#define R9A09G057_CST_0_AHB_ATH_RESETN			63
+#define R9A09G057_CST_0_ATB_CA55_RESETN			64
+#define R9A09G057_CST_0_ATB_CM33_RESETN			65
+#define R9A09G057_CST_0_ATB_CR8_RESETN			66
+#define R9A09G057_CST_0_ATB_CST_RESETN			67
+#define R9A09G057_CST_0_AXI_SB_RESETN			68
+#define R9A09G057_CST_0_AXI_ETR_RESETN			69
+#define R9A09G057_CST_0_NTRST				70
+#define R9A09G057_CST_0_NPOTRST				71
+#define R9A09G057_SYC_0_RESETN				72
+#define R9A09G057_MHU_0_PRESETN				73
+#define R9A09G057_AXI_TZCDDR_0_PRESET0N			74
+#define R9A09G057_AXI_TZCDDR_0_PRESET1N			75
+#define R9A09G057_AXI_TZCDDR_0_ARESET0N			76
+#define R9A09G057_AXI_TZCDDR_0_ARESET1N			77
+#define R9A09G057_AXI_TZCDDR_0_ARESET2N			78
+#define R9A09G057_AXI_TZCDDR_0_ARESET3N			79
+#define R9A09G057_AXI_TZCDDR_0_ARESET4N			80
+#define R9A09G057_AXI_TZCDDR_1_PRESET0N			81
+#define R9A09G057_AXI_TZCDDR_1_PRESET1N			82
+#define R9A09G057_AXI_TZCDDR_1_ARESET0N			83
+#define R9A09G057_AXI_TZCDDR_1_ARESET1N			84
+#define R9A09G057_AXI_TZCDDR_1_ARESET2N			85
+#define R9A09G057_AXI_TZCDDR_1_ARESET3N			86
+#define R9A09G057_AXI_TZCDDR_1_ARESET4N			87
+#define R9A09G057_ACPU_AXI_RESETN			88
+#define R9A09G057_ACPU_PERI_DDR_AXI_RESETN		89
+#define R9A09G057_MCPU_AXI_RESETN			90
+#define R9A09G057_RCPU_AXI_RESETN			91
+#define R9A09G057_VIDEO0_AXI_RESETN			92
+#define R9A09G057_ACPU_PERI_VIDEO0_AXI_RESETN		93
+#define R9A09G057_VIDEO1_AXI_RESETN			94
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_RESETN		95
+#define R9A09G057_DRP_AXI_RESETN			96
+#define R9A09G057_ACPU_PERI_DRP0_AXI_RESETN		97
+#define R9A09G057_ACPU_PERI_DRP1_AXI_RESETN		98
+#define R9A09G057_COM_AXI_RESETN			99
+#define R9A09G057_ACPU_PERI_COM0_AXI_RESETN		100
+#define R9A09G057_ACPU_PERI_COM1_AXI_RESETN		101
+#define R9A09G057_GPT_0_RST_P_REG			102
+#define R9A09G057_GPT_0_RST_S_REG			103
+#define R9A09G057_GPT_1_RST_P_REG			104
+#define R9A09G057_GPT_1_RST_S_REG			105
+#define R9A09G057_POEGA_0_RST				106
+#define R9A09G057_POEGB_0_RST				107
+#define R9A09G057_POEGC_0_RST				108
+#define R9A09G057_POEGD_0_RST				109
+#define R9A09G057_POEGA_1_RST				110
+#define R9A09G057_POEGB_1_RST				111
+#define R9A09G057_POEGC_1_RST				112
+#define R9A09G057_POEGD_1_RST				113
+#define R9A09G057_CMTW_0_RST_M				114
+#define R9A09G057_CMTW_1_RST_M				115
+#define R9A09G057_CMTW_2_RST_M				116
+#define R9A09G057_CMTW_3_RST_M				117
+#define R9A09G057_CMTW_4_RST_M				118
+#define R9A09G057_CMTW_5_RST_M				119
+#define R9A09G057_CMTW_6_RST_M				120
+#define R9A09G057_CMTW_7_RST_M				121
+#define R9A09G057_GTM_0_PRESETZ				122
+#define R9A09G057_GTM_1_PRESETZ				123
+#define R9A09G057_GTM_2_PRESETZ				124
+#define R9A09G057_GTM_3_PRESETZ				125
+#define R9A09G057_GTM_4_PRESETZ				126
+#define R9A09G057_GTM_5_PRESETZ				127
+#define R9A09G057_GTM_6_PRESETZ				128
+#define R9A09G057_GTM_7_PRESETZ				129
+#define R9A09G057_WDT_0_RESET				130
+#define R9A09G057_WDT_1_RESET				131
+#define R9A09G057_WDT_2_RESET				132
+#define R9A09G057_WDT_3_RESET				133
+#define R9A09G057_RTC_0_RST_RTC				134
+#define R9A09G057_RTC_0_RST_RTC_V			135
+#define R9A09G057_RSPI_0_PRESETN			136
+#define R9A09G057_RSPI_0_TRESETN			137
+#define R9A09G057_RSPI_1_PRESETN			138
+#define R9A09G057_RSPI_1_TRESETN			139
+#define R9A09G057_RSPI_2_PRESETN			140
+#define R9A09G057_RSPI_2_TRESETN			141
+#define R9A09G057_RSCI_0_PRESETN			142
+#define R9A09G057_RSCI_0_TRESETN			143
+#define R9A09G057_RSCI_1_PRESETN			144
+#define R9A09G057_RSCI_1_TRESETN			145
+#define R9A09G057_RSCI_2_PRESETN			146
+#define R9A09G057_RSCI_2_TRESETN			147
+#define R9A09G057_RSCI_3_PRESETN			148
+#define R9A09G057_RSCI_3_TRESETN			149
+#define R9A09G057_RSCI_4_PRESETN			150
+#define R9A09G057_RSCI_4_TRESETN			151
+#define R9A09G057_RSCI_5_PRESETN			152
+#define R9A09G057_RSCI_5_TRESETN			153
+#define R9A09G057_RSCI_6_PRESETN			154
+#define R9A09G057_RSCI_6_TRESETN			155
+#define R9A09G057_RSCI_7_PRESETN			156
+#define R9A09G057_RSCI_7_TRESETN			157
+#define R9A09G057_RSCI_8_PRESETN			158
+#define R9A09G057_RSCI_8_TRESETN			159
+#define R9A09G057_RSCI_9_PRESETN			160
+#define R9A09G057_RSCI_9_TRESETN			161
+#define R9A09G057_SCIF_0_RST_SYSTEM_N			162
+#define R9A09G057_I3C_0_PRESETN				163
+#define R9A09G057_I3C_0_TRESETN				164
+#define R9A09G057_RIIC_8_MRST				165
+#define R9A09G057_RIIC_0_MRST				166
+#define R9A09G057_RIIC_1_MRST				167
+#define R9A09G057_RIIC_2_MRST				168
+#define R9A09G057_RIIC_3_MRST				169
+#define R9A09G057_RIIC_4_MRST				170
+#define R9A09G057_RIIC_5_MRST				171
+#define R9A09G057_RIIC_6_MRST				172
+#define R9A09G057_RIIC_7_MRST				173
+#define R9A09G057_CANFD_0_RSTP_N			174
+#define R9A09G057_CANFD_0_RSTC_N			175
+#define R9A09G057_SPI_HRESETN				176
+#define R9A09G057_SPI_ARESETN				177
+#define R9A09G057_IOTOP_0_RESETN			178
+#define R9A09G057_IOTOP_0_ERROR_RESETN			179
+#define R9A09G057_SDHI_0_IXRST				180
+#define R9A09G057_SDHI_1_IXRST				181
+#define R9A09G057_SDHI_2_IXRST				182
+#define R9A09G057_USB30_RST_RESERVED0			183
+#define R9A09G057_USB31_RST_RESERVED0			184
+#define R9A09G057_USB20_RST_RESERVED0			185
+#define R9A09G057_USB21_RST_RESERVED0			186
+#define R9A09G057_USB20_USB21_RST_RESERVED0		187
+#define R9A09G057_USB20_USB21_RST_RESERVED1		188
+#define R9A09G057_GBETH0_RST_RESERVED0			189
+#define R9A09G057_GBETH1_RST_RESERVED0			190
+#define R9A09G057_PCIE_0_ARESETN			191
+#define R9A09G057_DDR0_RST_RESERVED0			192
+#define R9A09G057_DDR0_RST_RESERVED1			193
+#define R9A09G057_DDR0_RST_RESERVED2			194
+#define R9A09G057_DDR0_RST_RESERVED3			195
+#define R9A09G057_DDR0_RST_RESERVED4			196
+#define R9A09G057_DDR0_RST_RESERVED5			197
+#define R9A09G057_DDR0_RST_RESERVED6			198
+#define R9A09G057_DDR0_RST_RESERVED7			199
+#define R9A09G057_DDR0_RST_RESERVED8			200
+#define R9A09G057_DDR0_RST_RESERVED9			201
+#define R9A09G057_DDR1_RST_RESERVED0			202
+#define R9A09G057_DDR1_RST_RESERVED1			203
+#define R9A09G057_DDR1_RST_RESERVED2			204
+#define R9A09G057_DDR1_RST_RESERVED3			205
+#define R9A09G057_DDR1_RST_RESERVED4			206
+#define R9A09G057_DDR1_RST_RESERVED5			207
+#define R9A09G057_DDR1_RST_RESERVED6			208
+#define R9A09G057_DDR1_RST_RESERVED7			209
+#define R9A09G057_DDR1_RST_RESERVED8			210
+#define R9A09G057_DDR1_RST_RESERVED9			211
+#define R9A09G057_CRU_0_PRESETN				212
+#define R9A09G057_CRU_0_ARESETN				213
+#define R9A09G057_CRU_0_S_RESETN			214
+#define R9A09G057_CRU_1_PRESETN				215
+#define R9A09G057_CRU_1_ARESETN				216
+#define R9A09G057_CRU_1_S_RESETN			217
+#define R9A09G057_CRU_2_PRESETN				218
+#define R9A09G057_CRU_2_ARESETN				219
+#define R9A09G057_CRU_2_S_RESETN			220
+#define R9A09G057_CRU_3_PRESETN				221
+#define R9A09G057_CRU_3_ARESETN				222
+#define R9A09G057_CRU_3_S_RESETN			223
+#define R9A09G057_ISP_RST_RESERVED0			224
+#define R9A09G057_ISP_RST_RESERVED1			225
+#define R9A09G057_ISP_RST_RESERVED2			226
+#define R9A09G057_ISP_RST_RESERVED3			227
+#define R9A09G057_ISU_0_ARESETN				228
+#define R9A09G057_ISU_0_PRESETN				229
+#define R9A09G057_DSI_0_PRESETN				230
+#define R9A09G057_DSI_0_ARESETN				231
+#define R9A09G057_LCDC_0_RESET_N			232
+#define R9A09G057_GPU_0_RESETN				233
+#define R9A09G057_GPU_0_AXI_RESETN			234
+#define R9A09G057_GPU_0_ACE_RESETN			235
+#define R9A09G057_VCD_0_RESETN				236
+#define R9A09G057_SSIF_0_ASYNC_RESET_SSI		237
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI0		238
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI1		239
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI2		240
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI3		241
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI4		242
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI5		243
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI6		244
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI7		245
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI8		246
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI9		247
+#define R9A09G057_DMACPP_0_ARST				248
+#define R9A09G057_SCU_0_RESET_SRU			249
+#define R9A09G057_ADG_0_RST_RESET_ADG			250
+#define R9A09G057_SPDIF_0_RST				251
+#define R9A09G057_SPDIF_1_RST				252
+#define R9A09G057_SPDIF_2_RST				253
+#define R9A09G057_PDM_0_PRESETN				254
+#define R9A09G057_PDM_0_CRESETN				255
+#define R9A09G057_PDM_1_PRESETN				256
+#define R9A09G057_PDM_1_CRESETN				257
+#define R9A09G057_ADC_0_ADRST_N				258
+#define R9A09G057_TSU_0_PRESETN				259
+#define R9A09G057_TSU_1_PRESETN				260
+#define R9A09G057_OTPC_0_RESET_N			261
+#define R9A09G057_DRP_0_ARESETN				262
+#define R9A09G057_DRPAI_0_ARESETN			263
+
+#endif /* __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ */
-- 
2.34.1