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From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: <nm@ti.com>, <vigneshr@ti.com>, <afd@ti.com>, <kristo@kernel.org>,
        <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
        <rogerq@kernel.org>
CC: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <u-kumar1@ti.com>,
        <danishanwar@ti.com>, <srk@ti.com>, <s-vadapalli@ti.com>
Subject: [PATCH v3 4/7] arm64: dts: ti: k3-serdes: Add Serdes1 lane-muxing macros for J722S
Date: Fri, 24 May 2024 14:35:11 +0530
Message-ID: <20240524090514.152727-5-s-vadapalli@ti.com>
In-Reply-To: <20240524090514.152727-1-s-vadapalli@ti.com>
References: <20240524090514.152727-1-s-vadapalli@ti.com>
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The Serdes1 instance of the Serdes on J722S SoC is a single lane Serdes
that is muxed across PCIe and CPSW. Define the lane-muxing macros to be
used as the idle state values.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Current patch is v1. No changelog.

 arch/arm64/boot/dts/ti/k3-serdes.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index e6a036a4e70b..ef3606068140 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -206,4 +206,7 @@
 #define J722S_SERDES0_LANE0_USB			0x0
 #define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
 
+#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1
+
 #endif /* DTS_ARM64_TI_K3_SERDES_H */
-- 
2.40.1