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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 May 2024 12:25:18.7440 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f3f9ec1-2e2b-4199-565d-08dc7bec9313 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4085 If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured to track specific events. The event configuration is domain specific. ABMC (Assignable Bandwidth Monitoring Counters) feature needs event configuration information to assign hardware counter to an RMID. Event configurations are not stored in resctrl but instead always read from or written to hardware directly when prompted by user space. Read the event configuration from the hardware during the domain initialization. Save the configuration information in the rdt_hw_domain, so it can be used for counter assignment. Signed-off-by: Babu Moger --- v4: Read the configuration information from the hardware to initialize. Added few commit messages. Fixed the tab spaces. v3: Minor changes related to rebase in mbm_config_write_domain. v2: No changes. --- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/resctrl/internal.h | 5 +++++ arch/x86/kernel/cpu/resctrl/monitor.c | 21 +++++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index ec93f6a50308..856c46d12177 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -542,6 +542,8 @@ static void domain_add_cpu(int cpu, struct rdt_resource *r) return; } + arch_domain_mbm_evt_config(hw_dom); + list_add_tail_rcu(&d->list, add_pos); err = resctrl_online_domain(r, d); diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 5e7e76cd512f..60a1ca0a11a7 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -373,6 +373,8 @@ struct arch_mbm_state { * @ctrl_val: array of cache or mem ctrl values (indexed by CLOSID) * @arch_mbm_total: arch private state for MBM total bandwidth * @arch_mbm_local: arch private state for MBM local bandwidth + * @mbm_total_cfg: MBM total bandwidth configuration + * @mbm_local_cfg: MBM local bandwidth configuration * * Members of this structure are accessed via helpers that provide abstraction. */ @@ -381,6 +383,8 @@ struct rdt_hw_domain { u32 *ctrl_val; struct arch_mbm_state *arch_mbm_total; struct arch_mbm_state *arch_mbm_local; + u32 mbm_total_cfg; + u32 mbm_local_cfg; }; static inline struct rdt_hw_domain *resctrl_to_arch_dom(struct rdt_domain *r) @@ -622,6 +626,7 @@ void __check_limbo(struct rdt_domain *d, bool force_free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init resctrl_file_fflags_init(const char *config, unsigned long fflags); +void arch_domain_mbm_evt_config(struct rdt_hw_domain *hw_dom); void rdt_staged_configs_clear(void); bool closid_allocated(unsigned int closid); int resctrl_find_cleanest_closid(void); diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index b1d002e5e93d..ab0f4bb49bd9 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -1093,6 +1093,27 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) return 0; } +void arch_domain_mbm_evt_config(struct rdt_hw_domain *hw_dom) +{ + u64 msrval; + + /* + * Read the configuration registers QOS_EVT_CFG_n, where is + * the BMEC event number (EvtID). + * 0 for evtid == QOS_L3_MBM_TOTAL_EVENT_ID + * 1 for evtid == QOS_L3_MBM_LOCAL_EVENT_ID + */ + if (mbm_total_event.configurable) { + rdmsrl(MSR_IA32_EVT_CFG_BASE, msrval); + hw_dom->mbm_total_cfg = msrval & MAX_EVT_CONFIG_BITS; + } + + if (mbm_local_event.configurable) { + rdmsrl(MSR_IA32_EVT_CFG_BASE + 1, msrval); + hw_dom->mbm_local_cfg = msrval & MAX_EVT_CONFIG_BITS; + } +} + void __exit rdt_put_mon_l3_config(void) { dom_data_exit(); -- 2.34.1