Received: by 2002:a89:d88:0:b0:1fa:5c73:8e2d with SMTP id eb8csp539963lqb; Fri, 24 May 2024 06:21:08 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCWlzlzxrXsIiSHVtFy8CDQmdNbFAubx2Hf7QijIWqKFQc5/FnfMsffUaMZ9nhLIe47ZyQ/VErTPibR+PblbnJZOdQ3lvqfytHbySBRACA== X-Google-Smtp-Source: AGHT+IHGBhZ+lSgvSAk6HN8DZv3Q1iUbGqrywXLEoPeqGWbPC0TkiPChPXj+VWI4uyKoPKgCAFr5 X-Received: by 2002:a17:902:e5cd:b0:1ec:2e23:4c92 with SMTP id d9443c01a7336-1f448402115mr30755285ad.0.1716556867877; Fri, 24 May 2024 06:21:07 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1716556867; cv=pass; d=google.com; s=arc-20160816; b=qqoGEcSCsDqYjZdrIvBp25bNKuV1aHzF5OrGy82SPFAlO9+bfJvxHvdAP6SNNkTK2i ymqN9OrJsDcqeCzJumMLpnwXl+46SeydpVYZMnIxSnhDvgHecBLzMiBtPlFfAmJLNTp/ DtHa8yvhWXPGE2JdUXObud+xpX6nuteLdT3m28nZvaVgaz7jwvLilL+pJu5i0G/3PwXz 8fCtOGV8gGdpnp+EdS4sWJppJ5jy0HUjCxE+96fbuihLzPHLbN61SmYaPlMFt13o5Amy XHRJjKfrow8SYjHzoTP5CTKpxX0QunHZ6ijTM3jyUol6P9MwOvc67lGfE8mELdem7WJT MwmQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=6gTuD659RBNpe4VbArDAG26UrZnRn8ECIH/vQ20wfOg=; fh=lyLSCFSK6l9RW63ZDfr8yvsE4SO7J1cWsNA4C19DeNI=; b=k5UFWkncZyTpPwRm4l1m5nwJvfTyPuII0Ag/FHaY4v6UvmUvv1DAFIfqSfqeogeHJu FOpmG+ERalGfwc9fZfJfo9UjLaI9J5ybYl7HxZrZnMH0C7TVwVMkl4dlQ/UWcu6NHxmz v+jxXqw8UgQSaOKY7Ec+pEnNvbXYdbtCsfu0LpfNvBWe5t4Dqw+bZPQ6Q8hPH7Pcjxvl /MtlQACHhgzBVpX+wJYG3Szg7WRFGNJIZWrJXx7mq1n3O8/9xyOW4upavRY7TrhMEI2O pW6SWMhmPn06WQL+5A9VG90IFPJgz7Qxfv93+iV1xjrZ7LDuZDYqfj/cRzOkqNppIYoN pbtA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=n5w6FbmH; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-188727-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-188727-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [147.75.48.161]) by mx.google.com with ESMTPS id d9443c01a7336-1f44c785b65si13998875ad.41.2024.05.24.06.21.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 May 2024 06:21:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-188727-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=n5w6FbmH; arc=pass (i=1 spf=pass spfdomain=quicinc.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-188727-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-188727-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 8C9B8B217AA for ; Fri, 24 May 2024 13:20:46 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 973C312A172; Fri, 24 May 2024 13:19:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="n5w6FbmH" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B06E129E9E; Fri, 24 May 2024 13:19:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716556762; cv=none; b=rfIMmmAJsIOLUwSC3dFTaAHTf4UUGedImQSxO4ScjLGHYxgar8SxQpWoJKc7fzD+wXZMG0zbR7Qg8Hso5CXszqBcBwbtJbqROpFpEalSxsCVxrWoLssqVUqUrOkW+n+ZxAHIAjs/Y9C9hvFyAvdIUIWZN0e3NCCuVZPUoy7lg7c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716556762; c=relaxed/simple; bh=VYASND7DkjxIdSKvksdElZNKwr1G8BS4C2AWVcyC9ZM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=o+hahx48YSTZc9mXcWvQxW9vVyZlJnq7xc13zdRd2N/qYdQZVWk1KirOywo8Qe1eTN9ivR9p52Y5WVn/CCRT/QbgACmMpBIzJsrowFBNf5+SCFKC7nRsZrLrKvNAJDYAD2MKFSvQkogM6M6HXIs3hW+HN8Jkah8vvyNmjx+3wrU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=n5w6FbmH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 44O9GDo7004833; Fri, 24 May 2024 13:19:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 6gTuD659RBNpe4VbArDAG26UrZnRn8ECIH/vQ20wfOg=; b=n5w6FbmHG0RqjXtJ /YruTIKMv28FyHcTnggWHzOp1we1i2yTdk3Dk4rDjieGzDmufG7tAlz28JSgyqS0 388YRv96G2OfQLRqmst5unNOzFOHaaTBpbTEl093jBjD3g5yIoQfnR3h4ckz1NJ+ a7Am+UBumX6E3qMOQiSkZy+yLpCV+uRcZk7wGp/P9aZcGx6dfg7aI82B0igHKE19 /3KkW65eev16LLR5YmhiOPCtPJsLSINU+ZtU63Wex8JQ3DW3HKatDhVhseDmXido CIbJ8sp7TxakmAuNLtVgoqw7Q4P+aGisAtQm/ieOMp3iuyFWJ/tFv76O7MLmNmVZ dxqJYQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3yaa96jj4w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 May 2024 13:19:04 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 44ODJ3am031240 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 24 May 2024 13:19:03 GMT Received: from hu-bibekkum-hyd.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 24 May 2024 06:18:58 -0700 From: Bibek Kumar Patro To: , , , , , , , , , , CC: , , , , "Bibek Kumar Patro" Subject: [PATCH v10 5/5] iommu/arm-smmu: add ACTLR data and support for SC7280 Date: Fri, 24 May 2024 18:48:00 +0530 Message-ID: <20240524131800.2288259-6-quic_bibekkum@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240524131800.2288259-1-quic_bibekkum@quicinc.com> References: <20240524131800.2288259-1-quic_bibekkum@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qm4KlVUOxpQk-gZDHVmp0XsvZn83cYFY X-Proofpoint-ORIG-GUID: qm4KlVUOxpQk-gZDHVmp0XsvZn83cYFY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-24_04,2024-05-24_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 bulkscore=0 phishscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2405240091 Add ACTLR data table for SC7280 along with support for same including SC7280 specific implementation operations. Signed-off-by: Bibek Kumar Patro --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 35 +++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b4521471ffe9..8dabc26fa10e 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -29,6 +29,32 @@ #define PREFETCH_MODERATE (2 << PREFETCH_SHIFT) #define PREFETCH_DEEP (3 << PREFETCH_SHIFT) +static const struct actlr_config sc7280_apps_actlr_cfg[] = { + { 0x0800, 0x24e1, PREFETCH_DEFAULT | CMTLB }, + { 0x2000, 0x0163, PREFETCH_DEFAULT | CMTLB }, + { 0x2080, 0x0461, PREFETCH_DEFAULT | CMTLB }, + { 0x2100, 0x0161, PREFETCH_DEFAULT | CMTLB }, + { 0x0900, 0x0407, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x2180, 0x0027, PREFETCH_SHALLOW | CPRE | CMTLB }, + { 0x1000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB }, +}; + +static const struct actlr_config sc7280_gfx_actlr_cfg[] = { + { 0x0000, 0x07ff, PREFETCH_DEEP | CPRE | CMTLB }, +}; + +static const struct actlr_variant sc7280_actlr[] = { + { + .io_start = 0x15000000, + .actlrcfg = sc7280_apps_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sc7280_apps_actlr_cfg) + }, { + .io_start = 0x03da0000, + .actlrcfg = sc7280_gfx_actlr_cfg, + .num_actlrcfg = ARRAY_SIZE(sc7280_gfx_actlr_cfg) + }, +}; + static const struct actlr_config sm8550_apps_actlr_cfg[] = { { 0x18a0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, { 0x18e0, 0x0000, PREFETCH_SHALLOW | CPRE | CMTLB }, @@ -685,6 +711,13 @@ static const struct qcom_smmu_match_data sdm845_smmu_500_data = { /* Also no debug configuration. */ }; +static const struct qcom_smmu_match_data sc7280_smmu_500_impl0_data = { + .impl = &qcom_smmu_500_impl, + .adreno_impl = &qcom_adreno_smmu_500_impl, + .cfg = &qcom_smmu_impl0_cfg, + .actlrvar = sc7280_actlr, + .num_smmu = ARRAY_SIZE(sc7280_actlr), +}; static const struct qcom_smmu_match_data sm8550_smmu_500_impl0_data = { .impl = &qcom_smmu_500_impl, @@ -711,7 +744,7 @@ static const struct of_device_id __maybe_unused qcom_smmu_impl_of_match[] = { { .compatible = "qcom,qdu1000-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc7180-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc7180-smmu-v2", .data = &qcom_smmu_v2_data }, - { .compatible = "qcom,sc7280-smmu-500", .data = &qcom_smmu_500_impl0_data }, + { .compatible = "qcom,sc7280-smmu-500", .data = &sc7280_smmu_500_impl0_data }, { .compatible = "qcom,sc8180x-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sc8280xp-smmu-500", .data = &qcom_smmu_500_impl0_data }, { .compatible = "qcom,sdm630-smmu-v2", .data = &qcom_smmu_v2_data }, -- 2.34.1