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bh=GV/QsjEvDtrhh/ZaXZqdvmVcpw7ReZRze9VGzicNnAo=; b=3KCexhg73Y03UA5lUAYDBBkSIo TvXOKhmEyaz7DCfsb4AyRCFL5tGRInrmjgxHjCvr6TgT9JnO06oCPnAi67Z1dbri4Dl7kQnnY0wPz xMpBpvyU/DG6ql12hp9znHX1F6QfUBjXz2RvfaQstu7sWYlgWDmbzrH7RiiVsVveCg84=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1sAWFp-00FxZ4-Kb; Fri, 24 May 2024 16:50:45 +0200 Date: Fri, 24 May 2024 16:50:45 +0200 From: Andrew Lunn To: =?iso-8859-1?Q?Ram=F3n?= Nordin Rodriguez Cc: hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, parthiban.veerasooran@microchip.com Subject: Re: [PATCH net 0/1] phy: microchip_t1s: lan865x rev.b1 support Message-ID: <99f56020-9293-4e6b-8c2a-986af8c3dd79@lunn.ch> References: <20240524140706.359537-1-ramon.nordin.rodriguez@ferroamp.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240524140706.359537-1-ramon.nordin.rodriguez@ferroamp.se> > Far as I can tell the phy-driver cannot access some of the regs necessary > for probing the hardware and performing the init/fixup without going > over the spi interface. > The MMDCTRL register (used with indirect access) can address > > * PMA - mms 3 > * PCS - mms 2 > * Vendor specific / PLCA - mms 4 > > This driver needs to access mms (memory map seleector) > * mac registers - mms 1, > * vendor specific / PLCA - mms 4 > * vencor specific - mms 10 In general, a MAC should not be touching the PHY, and the PHY should not be touching the MAC. This rule is because you should not assume you have a specific MAC+PHY pair. However, this is one blob of silicon, so we can relax that a bit if needed. So it sounds like Microchip have mixed up the register address spaces :-( I guess this also means there is no discrete version of this PHY, because where would these registers be? Do any of the registers in the wrong address space need to be poked at runtime? By that i mean config_aneg(), read_status(). Or are they only needed around the time the PHY is probed? How critical is the ordering? Could we have the Microchip MAC driver probe. It instantiates the TC6 framework which registers the MDIO bus and probes the PHY. Can the MAC driver then complete the PHY setup using the registers in the wrong address space? Does it need to access any PHY registers in the correct address space? The MAC driver should be able to do this before phy_start() Does MMS 0 register 1 "PHY Identification Register" give enough information to know it is a B1 PHY? The standard suggests it is a straight copy of PHY registers 2 and 3. So the MAC driver does not need to touch PHY registers, we are not totally violating the layering... Andrew