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Message-ID: <986ff09f-212c-4905-ab06-35f85e20e9cf@web.de>
Date: Fri, 24 May 2024 17:35:42 +0200
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Subject: Re: [PATCH v3 6/7] PCI: xilinx-nwl: Add phy support
To: Sean Anderson <sean.anderson@linux.dev>,
 linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
 kernel-janitors@vger.kernel.org, =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?=
 <kw@linux.com>, Lorenzo Pieralisi <lpieralisi@kernel.org>,
 Rob Herring <robh@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
 Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>,
 Bjorn Helgaas <bhelgaas@google.com>,
 Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
 Michal Simek <michal.simek@amd.com>, Michal Simek <michal.simek@xilinx.com>,
 Thippeswamy Havalige <thippeswamy.havalige@amd.com>
References: <20240520145402.2526481-7-sean.anderson@linux.dev>
 <89d6acd5-5008-4db3-927c-d267be7b9302@web.de>
 <ad8da38a-5e3d-4f79-8744-66acf73703af@linux.dev>
Content-Language: en-GB
From: Markus Elfring <Markus.Elfring@web.de>
In-Reply-To: <ad8da38a-5e3d-4f79-8744-66acf73703af@linux.dev>
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>> =E2=80=A6
>>> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
>> =E2=80=A6
>>> @@ -818,12 +876,15 @@ static int nwl_pcie_probe(struct platform_device=
 *pdev)
>>>  		err =3D nwl_pcie_enable_msi(pcie);
>>>  		if (err < 0) {
>>>  			dev_err(dev, "failed to enable MSI support: %d\n", err);
>>> -			goto err_clk;
>>> +			goto err_phy;
>>>  		}
>>>  	}
>>>
>>>  	err =3D pci_host_probe(bridge);
>>>
>>> +err_phy:
>>> +	if (err)
>>> +		nwl_pcie_phy_disable(pcie);
>>>  err_clk:
>>>  	if (err)
>>>  		clk_disable_unprepare(pcie->clk);
>>
>> I got the impression that some source code adjustments should be perfor=
med
>> in another separate update step for this function implementation.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree=
/Documentation/process/submitting-patches.rst?h=3Dv6.9#n81
>>
>> You propose to extend the exception handling here.
>> Does such information indicate a need for another tag =E2=80=9CFixes=E2=
=80=9D?
>
> Huh? I am only disabling what I enabled...

* Was a resource deactivation accidentally missing in a previous release
  of this software component?

* Can repeated checks be avoided a bit more by a design approach which we =
tried
  to clarify for the update step =E2=80=9C[PATCH v3 5/7] PCI: xilinx-nwl: =
Clean up clock
  on probe failure/removal=E2=80=9D?
  https://lore.kernel.org/lkml/bb9e239f-902b-4f52-a5e9-98c29b360418@linux.=
dev/


Regards,
Markus