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Date: Sat, 25 May 2024 16:50:19 +0100
From: Conor Dooley <conor@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Magnus Damm <magnus.damm@gmail.com>,
	linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC
 CPG driver
Message-ID: <20240525-filling-revolving-307de19dd4c5@spud>
References: <20240524082800.333991-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
 <20240524082800.333991-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
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On Fri, May 24, 2024 at 09:27:57AM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>=20
> Document the device tree bindings of the Renesas RZ/V2H(P) SoC
> Clock Pulse Generator (CPG).
>=20
> CPG block handles the below operations:
> - Handles the generation and control of clock signals for the IP modules
> - The generation and control of resets
> - Control over booting
> - Low power consumption and the power supply domains
>=20
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/clock/renesas,rzv2h-cpg.yaml     | 78 +++++++++++++++++++
>  1 file changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h=
-cpg.yaml
>=20
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.ya=
ml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> new file mode 100644
> index 000000000000..baa0f2a5b6f9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
> +
> +maintainers:
> +  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +
> +description: |
> +  On Renesas RZ/V2H(P) SoC's, the CPG (Clock Pulse Generator) handles th=
e generation
> +  and control of clock signals for the IP modules, the generation and co=
ntrol of resets,
> +  and control over booting, low power consumption and the power supply d=
omains.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g057-cpg
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    description:
> +      Clock source to CPG can be either from external clock input (EXCLK=
) or
> +      crystal oscillator (XIN/XOUT).

I think this description should be in clocks, not clock names.

> +    const: extal
> +
> +  '#clock-cells':
> +    description: |
> +      - For CPG core clocks, the two clock specifier cells must be "CPG_=
CORE"
> +        and a core clock reference, as defined in
> +        <dt-bindings/clock/r9a09g057-cpg.h>,
> +      - For module clocks, the two clock specifier cells must be "CPG_MO=
D" and
> +        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.=
h>.

Can you please explain the difference and why it matters? Why isn't the
unique number for a given clock sufficient?

Thanks,
Conor.

> +    const: 2
> +
> +  '#power-domain-cells':
> +    description:
> +      SoC devices that are part of the CPG/Module Standby Mode Clock Dom=
ain and
> +      can be power-managed through Module Standby should refer to the CP=
G device
> +      node in their "power-domains" property, as documented by the gener=
ic PM
> +      Domain bindings in Documentation/devicetree/bindings/power/power-d=
omain.yaml.
> +      The power domain specifiers defined in <dt-bindings/clock/r9a09g05=
7-cpg.h> could
> +      be used to reference individual CPG power domains.
> +
> +  '#reset-cells':
> +    description:
> +      The single reset specifier cell must be the module number, as defi=
ned in
> +      <dt-bindings/clock/r9a09g057-cpg.h>.
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#power-domain-cells'
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    cpg: clock-controller@10420000 {
> +            compatible =3D "renesas,r9a09g057-cpg";
> +            reg =3D <0x10420000 0x10000>;
> +            clocks =3D <&extal_clk>;
> +            clock-names =3D "extal";
> +            #clock-cells =3D <2>;
> +            #power-domain-cells =3D <0>;
> +            #reset-cells =3D <1>;
> +    };
> --=20
> 2.34.1
>=20

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