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[2001:14ba:a0c3:3a00::227]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5297066b21dsm526727e87.173.2024.05.27.02.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 02:12:01 -0700 (PDT) Date: Mon, 27 May 2024 12:12:00 +0300 From: Dmitry Baryshkov To: Abel Vesa Cc: Vinod Koul , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Kuogee Hsieh Subject: Re: [PATCH 1/3] phy: qcom-qmp: qserdes-txrx: Add missing registers offsets Message-ID: References: <20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-0-be8a0b882117@linaro.org> <20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org> On Mon, May 27, 2024 at 10:20:35AM +0300, Abel Vesa wrote: > Currently, the x1e80100 uses pure V6 register offsets for DP part of the > combo PHY. This hasn't been an issue because external DP is not yet > enabled on any of the boards yet. But in order to enabled it, all these Nit: '...in order to enable it' > new V6 N4 register offsets are needed. So add them. > > Fixes: 762c3565f3c8 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets") > Co-developed-by: Kuogee Hsieh > Signed-off-by: Kuogee Hsieh > Signed-off-by: Abel Vesa > --- > drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_n4.h | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry