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Date: Mon, 27 May 2024 12:12:51 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Abel Vesa <abel.vesa@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>, 
	Kishon Vijay Abraham I <kishon@kernel.org>, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, 
	linux-kernel@vger.kernel.org, Kuogee Hsieh <quic_khsieh@quicinc.com>
Subject: Re: [PATCH 2/3] phy: qcom-qmp: pcs: Add missing v6 N4 register
 offsets
Message-ID: <n4mqyer56b6nnt7oce7bsdsjntws6alqkyqu7dw55btnutv7m5@gzuzigwkw3ld>
References: <20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-0-be8a0b882117@linaro.org>
 <20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org>
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In-Reply-To: <20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org>

On Mon, May 27, 2024 at 10:20:36AM +0300, Abel Vesa wrote:
> The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for
> combo USB and DP PHY.  Currently, the X1E80100 uses the pure V6 PCS
> register offsets, which are different. Add the offsets so the
> mentioned platform can be fixed later on. Add the new PCS offsets
> in a dedicated header file.
> 
> Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
> Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6-n4.h | 32 +++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry