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From: "Wang, Xiao W" <xiao.w.wang@intel.com>
To: Qingfang Deng <dqfext@gmail.com>, Paul Walmsley
	<paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou
	<aou@eecs.berkeley.edu>, "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>
CC: Qingfang Deng <qingfang.deng@siflower.com.cn>
Subject: RE: [PATCH v2] riscv: lib: relax assembly constraints in hweight
Thread-Topic: [PATCH v2] riscv: lib: relax assembly constraints in hweight
Thread-Index: AQHasBesp4ThaqJ1FEqryEoDIMEN07Gq32yA
Date: Mon, 27 May 2024 10:23:12 +0000
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References: <20240527092405.134967-1-dqfext@gmail.com>
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> -----Original Message-----
> From: Qingfang Deng <dqfext@gmail.com>
> Sent: Monday, May 27, 2024 5:24 PM
> To: Paul Walmsley <paul.walmsley@sifive.com>; Palmer Dabbelt
> <palmer@dabbelt.com>; Albert Ou <aou@eecs.berkeley.edu>; linux-
> riscv@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: Wang, Xiao W <xiao.w.wang@intel.com>; Qingfang Deng
> <qingfang.deng@siflower.com.cn>
> Subject: [PATCH v2] riscv: lib: relax assembly constraints in hweight
>=20
> From: Qingfang Deng <qingfang.deng@siflower.com.cn>
>=20
> rd and rs don't have to be the same. In some cases where rs needs to be
> saved for later usage, this will save us some mv instructions.
>=20
> Signed-off-by: Qingfang Deng <qingfang.deng@siflower.com.cn>
> ---
> v2: updated title as suggested by Xiao.
>=20
>  arch/riscv/include/asm/arch_hweight.h | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>=20
> diff --git a/arch/riscv/include/asm/arch_hweight.h
> b/arch/riscv/include/asm/arch_hweight.h
> index 85b2c443823e..613769b9cdc9 100644
> --- a/arch/riscv/include/asm/arch_hweight.h
> +++ b/arch/riscv/include/asm/arch_hweight.h
> @@ -26,9 +26,9 @@ static __always_inline unsigned int
> __arch_hweight32(unsigned int w)
>=20
>  	asm (".option push\n"
>  	     ".option arch,+zbb\n"
> -	     CPOPW "%0, %0\n"
> +	     CPOPW "%0, %1\n"
>  	     ".option pop\n"
> -	     : "+r" (w) : :);
> +	     : "=3Dr" (w) : "r" (w) :);
>=20
>  	return w;
>=20
> @@ -57,9 +57,9 @@ static __always_inline unsigned long
> __arch_hweight64(__u64 w)
>=20
>  	asm (".option push\n"
>  	     ".option arch,+zbb\n"
> -	     "cpop %0, %0\n"
> +	     "cpop %0, %1\n"
>  	     ".option pop\n"
> -	     : "+r" (w) : :);
> +	     : "=3Dr" (w) : "r" (w) :);
>=20
>  	return w;
>=20
> --
> 2.34.1

Reviewed-by: Xiao Wang <xiao.w.wang@intel.com>