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AJvYcCXfgbdUYWyaKc4v8+7VusAXTKe+Ea/YVxEJKw7eP95kd74IprKBcdJRN4s3yOPyFbEHOOSkhf0odJ8DwxiFWc8KZKyNG+QVWx9Jua0n X-Gm-Message-State: AOJu0YztajFdIpkIleTv4SqVreH9n4MQ/v0wpDAtMLR8+EyHL558eV7e hjPJ25QyIiDU0mSPTq8ZfKDUDOeY30+09G88kMH+BYnXcwLxX9+/l6gCbKi/mOLq6Fb6ObOchYW mzTQen6IP9SUfcob16b7J4wUuMdmh9vMk+A4wjw== X-Received: by 2002:a25:ced3:0:b0:df4:d5f4:3ef2 with SMTP id 3f1490d57ef6-df77218adb9mr8965780276.20.1716807956744; Mon, 27 May 2024 04:05:56 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240506-imx-pinctrl-optional-v2-0-bdff75085156@geanix.com> In-Reply-To: <20240506-imx-pinctrl-optional-v2-0-bdff75085156@geanix.com> From: Linus Walleij Date: Mon, 27 May 2024 13:05:45 +0200 Message-ID: Subject: Re: [PATCH v2 0/3] ARM: imx: only enable pinctrl as needed To: Esben Haabendal Cc: Russell King , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dong Aisheng , Jacky Bai , Arnd Bergmann , Rasmus Villemoes , linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, May 6, 2024 at 12:24=E2=80=AFPM Esben Haabendal = wrote: > As not all mach-imx platforms has support for run-time changes of pin > configurations (such as LS1021A), a more selective approach to enabling > pinctrl infrastructure makes sense, so that an e.g. an LS1021A only kerne= l > could be built without pinctrl support. > > This is a very late follow up v1 3 years ago [1]. The situation seems to = be > unchanged since then, and I have tried to incorporate the requested > changes. What is the verdict from the i.MX pin control maintainers on this? I can merge this into the pin control tree for v6.11 but it'd be nice to get an ACK from the maintainers first. Yours, Linus Walleij