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Date: Mon, 27 May 2024 14:24:40 +0200
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Subject: Re: [PATCH v1 1/2] dt-bindings: PCI: microchip,pcie-host: fix reg
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To: Conor Dooley <conor.dooley@microchip.com>
Cc: conor@kernel.org, Daire McNamara <daire.mcnamara@microchip.com>,
 Lorenzo Pieralisi <lpieralisi@kernel.org>,
 =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= <kw@linux.com>,
 Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
 Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley
 <conor+dt@kernel.org>, linux-pci@vger.kernel.org,
 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
 linux-riscv@lists.infradead.org
References: <20240527-slather-backfire-db4605ae7cd7@wendy>
 <20240527-algebra-pencil-c12962d62468@wendy>
From: Krzysztof Kozlowski <krzk@kernel.org>
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In-Reply-To: <20240527-algebra-pencil-c12962d62468@wendy>
Content-Type: text/plain; charset=UTF-8
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On 27/05/2024 11:37, Conor Dooley wrote:
> The PCI host controller on PolarFire SoC has multiple "instances", each
> with their own bridge and ctrl address spaces. The original binding has
> an "apb" register region, and it is expected to be set to the base
> address of the host controllers register space. Some defines in the
> Linux driver were used to compute the addresses of the bridge and ctrl
> address ranges corresponding to instance1. Some customers want to use
> instance2 however and that requires changing the defines in the driver,
> which is clearly not a portable solution.
> 
> Remove this "apb" register region from the binding and add "bridge" &
> "ctrl" regions instead, that will directly communicate the address of
> these regions
> 
> Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  .../devicetree/bindings/pci/microchip,pcie-host.yaml   | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof