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Date: Tue, 28 May 2024 18:10:53 +0530
From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Roger Quadros <rogerq@kernel.org>
CC: Siddharth Vadapalli <s-vadapalli@ti.com>, <nm@ti.com>, <vigneshr@ti.com>,
        <afd@ti.com>, <kristo@kernel.org>, <robh@kernel.org>,
        <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <u-kumar1@ti.com>,
        <danishanwar@ti.com>, <srk@ti.com>
Subject: Re: [PATCH v3 4/7] arm64: dts: ti: k3-serdes: Add Serdes1
 lane-muxing macros for J722S
Message-ID: <2aaf80f4-2631-4a3c-a4cb-394776764801@ti.com>
References: <20240524090514.152727-1-s-vadapalli@ti.com>
 <20240524090514.152727-5-s-vadapalli@ti.com>
 <def2fd41-371a-4b2a-925d-81b149aaae01@kernel.org>
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On Tue, May 28, 2024 at 03:19:30PM +0300, Roger Quadros wrote:
> 
> 
> On 24/05/2024 12:05, Siddharth Vadapalli wrote:
> > The Serdes1 instance of the Serdes on J722S SoC is a single lane Serdes
> > that is muxed across PCIe and CPSW. Define the lane-muxing macros to be
> > used as the idle state values.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > Current patch is v1. No changelog.
> > 
> >  arch/arm64/boot/dts/ti/k3-serdes.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> > index e6a036a4e70b..ef3606068140 100644
> > --- a/arch/arm64/boot/dts/ti/k3-serdes.h
> > +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> > @@ -206,4 +206,7 @@
> >  #define J722S_SERDES0_LANE0_USB			0x0
> >  #define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
> >  
> > +#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0
> > +#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1
> > +
> 
> Maybe this one patch can deal with both USB and PCIE0 additions to this file
> and could be moved earlier in the series.

Yes. I will combine this with the SERDES0 changes in the v4 series.

Regards,
Siddharth.