Received-SPF: pass (google.com: domain of linux-kernel+bounces-192325-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1;
Date: Tue, 28 May 2024 18:14:08 +0530
From: Siddharth Vadapalli <s-vadapalli@ti.com>
To: Roger Quadros <rogerq@kernel.org>
CC: Siddharth Vadapalli <s-vadapalli@ti.com>, <nm@ti.com>, <vigneshr@ti.com>,
        <afd@ti.com>, <kristo@kernel.org>, <robh@kernel.org>,
        <krzk+dt@kernel.org>, <conor+dt@kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <u-kumar1@ti.com>,
        <danishanwar@ti.com>, <srk@ti.com>
Subject: Re: [PATCH v3 7/7] arm64: dts: ti: k3-j722s: Add support for PCIe0
Message-ID: <ff6cb81b-7760-4c99-9c17-907b0a31396c@ti.com>
References: <20240524090514.152727-1-s-vadapalli@ti.com>
 <20240524090514.152727-8-s-vadapalli@ti.com>
 <a6fe1fbe-681d-429b-99cc-a5f07af1cd15@kernel.org>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <a6fe1fbe-681d-429b-99cc-a5f07af1cd15@kernel.org>

On Tue, May 28, 2024 at 03:26:11PM +0300, Roger Quadros wrote:

[...]

> >  
> > +#include <dt-bindings/phy/phy-cadence.h>
> >  #include <dt-bindings/phy/phy-ti.h>
> >  
> >  /*
> > @@ -96,6 +97,35 @@ serdes1: serdes@f010000 {
> >  		};
> >  	};
> >  
> > +	pcie0_rc: pcie@f102000 {
> 
> Please split PCIe node addition in  to separate patch. hopefully you can squash it with patches that
> add USB, SERDES0 and SERDES1 to k3-j722s-main.dtsi.

I will do so in the v4 series. Thank you for reviewing and sharing your
feedback on this series.

Regards,
Siddharth.