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[209.85.208.176]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2e98446942csm3616421fa.8.2024.05.28.09.06.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 May 2024 09:06:46 -0700 (PDT) Received: by mail-lj1-f176.google.com with SMTP id 38308e7fff4ca-2e95a60dfcdso11271241fa.1; Tue, 28 May 2024 09:06:46 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCV/wauuiRHgt92ywtyEM7JPaT/cmd9Ae1r2RVR7R28YzakQM3fPPM7Xf1QiGrP7bknKZO9Mct4d+ZwrTKTnQgUVmyoOzGbUGKGMCDzs/55sxyolhUXwKY/zTUQJBUEIsQ4LFEP9Op+QiQ== X-Received: by 2002:a2e:2e0d:0:b0:2e9:5966:790a with SMTP id 38308e7fff4ca-2e95b1cc478mr74542041fa.15.1716912406795; Tue, 28 May 2024 09:06:46 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <6a772756c2c677dbdaaab4a2c71a358d8e4b27e9.1714304058.git.dsimic@manjaro.org> <49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org> <171691117471.681554.6744393893618279840.b4-ty@csie.org> <803a939c62b3ac4ced7ac49f18efd723@manjaro.org> In-Reply-To: <803a939c62b3ac4ced7ac49f18efd723@manjaro.org> Reply-To: wens@csie.org From: Chen-Yu Tsai Date: Wed, 29 May 2024 00:06:34 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 To: Dragan Simic Cc: jernej.skrabec@gmail.com, samuel@sholland.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, May 29, 2024 at 12:02=E2=80=AFAM Dragan Simic = wrote: > > Hello Chen-Yu, > > On 2024-05-28 17:56, Chen-Yu Tsai wrote: > > On Tue, May 28, 2024 at 11:46=E2=80=AFPM Chen-Yu Tsai w= rote: > >> > >> On Sun, 28 Apr 2024 13:40:36 +0200, Dragan Simic wrote: > >> > Add missing cache information to the Allwinner H6 SoC dtsi, to allow > >> > the userspace, which includes lscpu(1) that uses the virtual files p= rovided > >> > by the kernel under the /sys/devices/system/cpu directory, to displa= y the > >> > proper H6 cache information. > >> > > >> > Adding the cache information to the H6 SoC dtsi also makes the follo= wing > >> > warning message in the kernel log go away: > >> > > >> > [...] > >> > >> Applied to sunxi/dt-for-6.11 in sunxi/linux.git, thanks! > >> > >> [1/1] arm64: dts: allwinner: Add cache information to the SoC dtsi for > >> H6 > >> https://git.kernel.org/sunxi/linux/c/c8240e4b0fd2 > > > > OK, that's weird. Somehow b4 thought this patch was v2 of the A64 patch > > [1]. > > Looks like they are threaded together because this patch has > > "In-Reply-To". > > > > Please avoid it in the future. > > I'm sorry for that. I noticed that back when I sent the patches to the > mailing list, but didn't want to make some noise about that. The root > cause was some missing configuration for "git send-email", which > resulted > in adding troublesome threading-related headers to the messages for the > individual .patch files that in fact were correctly created by running > "git format-patch". > > Do I need to resend the patches? No. I figured it out.