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From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Date: Tue, 28 May 2024 20:15:54 +0100
Message-ID: <CA+V-a8uG+xBmDAvXRSDH2Qr8k9Xs-g6_bs+54Erc7_qqP=xLrg@mail.gmail.com>
Subject: Re: [PATCH v2 06/13] pinctrl: renesas: pinctrl-rzg2l: Add function
 pointers for locking/unlocking the PFC register
To: Biju Das <biju.das.jz@bp.renesas.com>, Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Linus Walleij <linus.walleij@linaro.org>, Rob Herring <robh@kernel.org>, 
	Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, 
	Magnus Damm <magnus.damm@gmail.com>, 
	"linux-renesas-soc@vger.kernel.org" <linux-renesas-soc@vger.kernel.org>, 
	"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>, 
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, 
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, 
	Fabrizio Castro <fabrizio.castro.jz@renesas.com>, 
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Content-Type: text/plain; charset="UTF-8"
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Hi Biju, Geert,

Thank you for the review.

On Wed, May 22, 2024 at 1:40=E2=80=AFPM Biju Das <biju.das.jz@bp.renesas.co=
m> wrote:
>
> Hi Geert,
>
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: Wednesday, May 22, 2024 1:23 PM
> > Subject: Re: [PATCH v2 06/13] pinctrl: renesas: pinctrl-rzg2l: Add func=
tion pointers for
> > locking/unlocking the PFC register
> >
> > Hi Biju,
> >
> > On Tue, Apr 23, 2024 at 8:12=E2=80=AFPM Biju Das <biju.das.jz@bp.renesa=
s.com> wrote:
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Tuesday, April 23, 2024 6:59 PM
> > > > Subject: [PATCH v2 06/13] pinctrl: renesas: pinctrl-rzg2l: Add
> > > > function pointers for locking/unlocking the PFC register
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > On the RZ/G2L SoC, the PFCWE bit controls writing to PFC registers.
> > > > However, on the RZ/V2H(P) SoC, the PFCWE (REGWE_A on RZ/V2H) bit
> > > > controls writing to both PFC and PMC registers. Additionally, BIT(7=
)
> > > > B0WI is undocumented for the PWPR register on RZ/V2H(P) SoC. To
> > > > accommodate these differences across SoC variants, introduce the
> > > > set_pfc_mode() and
> > > > pm_set_pfc() function pointers.
> > > >
> > > > Note, in rzg2l_pinctrl_set_pfc_mode() the pwpr_pfc_unlock() call is
> > > > now called before PMC read/write and pwpr_pfc_lock() call is now
> > > > called after PMC read/write this is to keep changes minimal for RZ/=
V2H(P).
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > RFC->v2
> > > > - Introduced function pointer for (un)lock
> >
> > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > @@ -2688,6 +2699,8 @@ static struct rzg2l_pinctrl_data r9a07g043_da=
ta =3D {
> > > >       .variable_pin_cfg =3D r9a07g043f_variable_pin_cfg,
> > > >       .n_variable_pin_cfg =3D ARRAY_SIZE(r9a07g043f_variable_pin_cf=
g),
> > > >  #endif
> > > > +     .pwpr_pfc_unlock =3D &rzg2l_pwpr_pfc_unlock,
> > > > +     .pwpr_pfc_lock =3D &rzg2l_pwpr_pfc_lock,
> > > >  };
> > > >
> > > >  static struct rzg2l_pinctrl_data r9a07g044_data =3D { @@ -2699,6
> > > > +2712,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data =3D {
> > > >       .n_dedicated_pins =3D ARRAY_SIZE(rzg2l_dedicated_pins.common)=
 +
> > > >               ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
> > > >       .hwcfg =3D &rzg2l_hwcfg,
> > > > +     .pwpr_pfc_unlock =3D &rzg2l_pwpr_pfc_unlock,
> > > > +     .pwpr_pfc_lock =3D &rzg2l_pwpr_pfc_lock,
> > > >  };
> > > >
> > > >  static struct rzg2l_pinctrl_data r9a08g045_data =3D { @@ -2709,6
> > > > +2724,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D {
> > > >       .n_port_pins =3D ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_P=
INS_PER_PORT,
> > > >       .n_dedicated_pins =3D ARRAY_SIZE(rzg3s_dedicated_pins),
> > > >       .hwcfg =3D &rzg3s_hwcfg,
> > > > +     .pwpr_pfc_unlock =3D &rzg2l_pwpr_pfc_unlock,
> > > > +     .pwpr_pfc_lock =3D &rzg2l_pwpr_pfc_lock,
> > >
> > > Some memory can be saved by avoiding duplication of data by using a
> > > single pointer for structure containing function pointers??
> > >
> > > struct rzg2l_pinctrl_fns {
> > >         void (*pwpr_pfc_unlock)(struct rzg2l_pinctrl *pctrl);
> > >         void (*pwpr_pfc_lock)(struct rzg2l_pinctrl *pctrl); }
> >
> > So that would replace 3 (4 after adding RZ/V2H support) x 2 pointers in=
 rzg2l_pinctrl_data
> > structures by 3 (4) pointers in rzg2l_pinctrl_data structures + 1 (2) x=
 2 pointers in
> > rzg2l_pinctrl_fns structures, and code size would increase due to extra=
 pointer dereferences before
> > each call.
> > Am I missing something?
>
> Current case
> 3 * 2 pointers =3D 6 pointers
>
> Suggestion
> 3 * 1 pointer + 1 * 2 pointer =3D 5 pointers
>
> As you said,  code size would increase due to extra pointer dereferences =
before
> each call.
>
>
> >
> > Merging rzg2l_pwpr_pfc_{,un}lock() into a single function (taking a "bo=
ol lock" flag) might be a
> > better solution to reduce rzg2l_pinctrl_data size.
>
> I agree.
>
OK, I will introduce a single function pointer (pwpr_pfc_lock_unlock)
in this patch.

Cheers,
Prabhakar