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Date: Wed, 29 May 2024 07:30:15 +0100
From: Conor Dooley <conor.dooley@microchip.com>
To: "Wang, Xiao W" <xiao.w.wang@intel.com>
CC: Conor Dooley <conor@kernel.org>, "linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>, Andrew Jones <ajones@ventanamicro.com>,
	"pulehui@huawei.com" <pulehui@huawei.com>, Charlie Jenkins
	<charlie@rivosinc.com>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer
 Dabbelt <palmer@dabbelt.com>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>, Samuel Holland <samuel.holland@sifive.com>,
	Pu Lehui <pulehui@huaweicloud.com>, =?iso-8859-1?Q?Bj=F6rn_T=F6pel?=
	<bjorn@kernel.org>
Subject: Re: [PATCH v3 2/2] RISC-V: separate Zbb optimisations requiring and
 not requiring toolchain support
Message-ID: <20240529-hangup-recipient-246586c6f8a8@wendy>
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On Wed, May 29, 2024 at 01:01:24AM +0000, Wang, Xiao W wrote:
> > From: Conor Dooley <conor@kernel.org>
> > Sent: Tuesday, May 28, 2024 7:11 PM
> > -	ALTERNATIVE("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB,
> > CONFIG_RISCV_ISA_ZBB)
> > +	__ALTERNATIVE_CFG("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB,
> > +		IS_ENABLED(CONFIG_RISCV_ISA_ZBB_ALT) &&
> > IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
>=20
> s/CONFIG_RISCV_ISA_ZBB_ALT/ CONFIG_RISCV_ISA_ZBB
> Same issue for below changes in strn*.S

I could have sworn I grepped for it and there was nothing, obviously
not... Thanks, I'll fix it up in a new version.

Thanks,
Conor

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