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References: <20240527093908.97574-1-angelogioacchino.delregno@collabora.com> <20240527093908.97574-6-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20240527093908.97574-6-angelogioacchino.delregno@collabora.com>
From: Chen-Yu Tsai <wenst@chromium.org>
Date: Wed, 29 May 2024 14:34:54 +0800
Message-ID: <CAGXv+5EbYBLt84Gx0mhTt9SqH8iMW87Y=_q=R2sHmJ4fygUQnQ@mail.gmail.com>
Subject: Re: [PATCH 5/5] arm64: dts: mediatek: mt8188: Add support for Mali
 GPU on Panfrost
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: linux-mediatek@lists.infradead.org, lee@kernel.org, robh@kernel.org, 
	krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, 
	mandyjh.liu@mediatek.com, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, 
	kernel@collabora.com, jpanis@baylibre.com
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On Mon, May 27, 2024 at 5:40=E2=80=AFPM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Add the necessary OPP table for the GPU and also add a GPU node
> to enable support for the Valhall-JM G57 MC3 found on this SoC,
> using the Panfrost driver.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@coll=
abora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8188.dtsi | 123 +++++++++++++++++++++++
>  1 file changed, 123 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/d=
ts/mediatek/mt8188.dtsi
> index 0bca6c9f15fe..29d012d28edb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -294,6 +294,112 @@ clk32k: oscillator-32k {
>                 clock-output-names =3D "clk32k";
>         };
>
> +       gpu_opp_table: opp-table-gpu {
> +               compatible =3D "operating-points-v2";
> +               opp-shared;
> +
> +               opp-390000000 {
> +                       opp-hz =3D /bits/ 64 <390000000>;
> +                       opp-microvolt =3D <575000>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-431000000 {
> +                       opp-hz =3D /bits/ 64 <431000000>;
> +                       opp-microvolt =3D <587500>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-473000000 {
> +                       opp-hz =3D /bits/ 64 <473000000>;
> +                       opp-microvolt =3D <600000>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-515000000 {
> +                       opp-hz =3D /bits/ 64 <515000000>;
> +                       opp-microvolt =3D <612500>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-556000000 {
> +                       opp-hz =3D /bits/ 64 <556000000>;
> +                       opp-microvolt =3D <625000>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-598000000 {
> +                       opp-hz =3D /bits/ 64 <598000000>;
> +                       opp-microvolt =3D <637500>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-640000000 {
> +                       opp-hz =3D /bits/ 64 <640000000>;
> +                       opp-microvolt =3D <650000>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-670000000 {
> +                       opp-hz =3D /bits/ 64 <670000000>;
> +                       opp-microvolt =3D <662500>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-700000000 {
> +                       opp-hz =3D /bits/ 64 <700000000>;
> +                       opp-microvolt =3D <675000>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-730000000 {
> +                       opp-hz =3D /bits/ 64 <730000000>;
> +                       opp-microvolt =3D <687500>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-760000000 {
> +                       opp-hz =3D /bits/ 64 <760000000>;
> +                       opp-microvolt =3D <700000>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-790000000 {
> +                       opp-hz =3D /bits/ 64 <790000000>;
> +                       opp-microvolt =3D <712500>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-835000000 {
> +                       opp-hz =3D /bits/ 64 <835000000>;
> +                       opp-microvolt =3D <731250>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-880000000 {
> +                       opp-hz =3D /bits/ 64 <880000000>;
> +                       opp-microvolt =3D <750000>;
> +                       opp-supported-hw =3D <0xff>;
> +               };
> +               opp-915000000 {
> +                       opp-hz =3D /bits/ 64 <915000000>;
> +                       opp-microvolt =3D <775000>;
> +                       opp-supported-hw =3D <0x8f>;
> +               };
> +               opp-915000000-5 {
> +                       opp-hz =3D /bits/ 64 <915000000>;
> +                       opp-microvolt =3D <762500>;
> +                       opp-supported-hw =3D <0x30>;
> +               };
> +               opp-915000000-6 {
> +                       opp-hz =3D /bits/ 64 <915000000>;
> +                       opp-microvolt =3D <750000>;
> +                       opp-supported-hw =3D <0x70>;
> +               };
> +               opp-950000000 {
> +                       opp-hz =3D /bits/ 64 <950000000>;
> +                       opp-microvolt =3D <800000>;
> +                       opp-supported-hw =3D <0x8f>;
> +               };
> +               opp-950000000-5 {
> +                       opp-hz =3D /bits/ 64 <950000000>;
> +                       opp-microvolt =3D <775000>;
> +                       opp-supported-hw =3D <0x30>;
> +               };
> +               opp-950000000-6 {
> +                       opp-hz =3D /bits/ 64 <950000000>;
> +                       opp-microvolt =3D <750000>;
> +                       opp-supported-hw =3D <0x70>;
> +               };
> +       };
> +
>         pmu-a55 {
>                 compatible =3D "arm,cortex-a55-pmu";
>                 interrupt-parent =3D <&gic>;
> @@ -1167,6 +1273,23 @@ imp_iic_wrap_en: clock-controller@11ec2000 {
>                         #clock-cells =3D <1>;
>                 };
>
> +               gpu: gpu@13000000 {
> +                       compatible =3D "mediatek,mt8188-mali", "arm,mali-=
valhall-jm";
> +                       reg =3D <0 0x13000000 0 0x4000>;
> +
> +                       clocks =3D <&mfgcfg CLK_MFGCFG_BG3D>;
> +                       interrupts =3D <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0=
>,
> +                                    <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       interrupt-names =3D "job", "mmu", "gpu";
> +                       operating-points-v2 =3D <&gpu_opp_table>;
> +                       power-domains =3D <&spm MT8188_POWER_DOMAIN_MFG2>=
,
> +                                       <&spm MT8188_POWER_DOMAIN_MFG3>,
> +                                       <&spm MT8188_POWER_DOMAIN_MFG4>;
> +                       power-domain-names =3D "core0", "core1", "core2";
> +                       status =3D "disabled";
> +               };
> +

This block no longer applies cleanly on the MTK tree because of
"arm64: dts: mediatek: mt8188: add lvts definitions" being applied.

ChenYu

>                 mfgcfg: clock-controller@13fbf000 {
>                         compatible =3D "mediatek,mt8188-mfgcfg";
>                         reg =3D <0 0x13fbf000 0 0x1000>;
> --
> 2.45.1
>
>