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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5995.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 35b88b9b-4b3f-4cdc-1d3a-08dc7fab1e0a X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2024 06:46:49.9745 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: nq8ZS+WsJZ2VF1zIlkALfEtUnG0Og4a/DmgGifTHmaUNPgTE/q2klEUDm6Ubmttm3XoG1lg66Ltly3hLxxrLsQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR11MB5818 X-OriginatorOrg: intel.com >-----Original Message----- >From: Arnd Bergmann >Sent: Tuesday, May 28, 2024 7:58 PM >To: Srinivas Pandruvada ; Jiri Kosina >; Benjamin Tissoires ; Zhang, Lixu > >Cc: Arnd Bergmann ; linux-input@vger.kernel.org; linux- >kernel@vger.kernel.org >Subject: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake > >From: Arnd Bergmann > >The low-level cache operation on a coherent buffer is incorrect, as cohere= nt >DMA memory may not actually be cached. Instead, use a DMA barrier that >ensures that the data is visible to the DMA master before the address is a= nd >move the memcpy() before the reference. > >Fixes: 579a267e4617 ("HID: intel-ish-hid: Implement loading firmware from >host feature") >Signed-off-by: Arnd Bergmann >--- >I noticed this one while looking at the bug that was fixed in >236049723826 ("HID: intel-ish-hid: Fix build error for COMPILE_TEST") >--- > drivers/hid/intel-ish-hid/ishtp/loader.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > >diff --git a/drivers/hid/intel-ish-hid/ishtp/loader.c b/drivers/hid/intel-= ish- >hid/ishtp/loader.c >index 2785b04a2f5a..062d1b25eaa7 100644 >--- a/drivers/hid/intel-ish-hid/ishtp/loader.c >+++ b/drivers/hid/intel-ish-hid/ishtp/loader.c >@@ -33,7 +33,6 @@ > > #define dev_fmt(fmt) "ISH loader: " fmt > >-#include > #include > #include > #include >@@ -175,10 +174,11 @@ static int prepare_dma_bufs(struct ishtp_device >*dev, > return -ENOMEM; > > fragment->fragment_tbl[i].ddr_adrs =3D >cpu_to_le64(dma_addr); >+ >+ memcpy(dma_bufs[i], ish_fw->data + offset, fragment- >>fragment_tbl[i].length); fragment->fragment_tbl[i].length was used before assignment. =20 >+ dma_wmb(); I tested it on the platform, but it didn't wok. Thanks, Lixu > fragment->fragment_tbl[i].length =3D clamp(ish_fw->size - >offset, 0, fragment_size); > fragment->fragment_tbl[i].fw_off =3D offset; >- memcpy(dma_bufs[i], ish_fw->data + offset, fragment- >>fragment_tbl[i].length); >- clflush_cache_range(dma_bufs[i], fragment_size); > > offset +=3D fragment->fragment_tbl[i].length; > } >-- >2.39.2