Received-SPF: pass (google.com: domain of linux-kernel+bounces-193683-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
From: Xu Yang <xu.yang_2@nxp.com>
To: frank.li@nxp.com,
	will@kernel.org,
	mark.rutland@arm.com,
	robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org,
	shawnguo@kernel.org,
	s.hauer@pengutronix.de,
	kernel@pengutronix.de,
	festevam@gmail.com,
	john.g.garry@oracle.com,
	jolsa@kernel.org,
	namhyung@kernel.org,
	irogers@google.com
Cc: mike.leach@linaro.org,
	peterz@infradead.org,
	mingo@redhat.com,
	acme@kernel.org,
	alexander.shishkin@linux.intel.com,
	adrian.hunter@intel.com,
	linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-perf-users@vger.kernel.org,
	imx@lists.linux.dev
Subject: [PATCH v12 5/8] perf: imx_perf: fix counter start and config sequence
Date: Wed, 29 May 2024 16:03:55 +0800
Message-Id: <20240529080358.703784-5-xu.yang_2@nxp.com>
In-Reply-To: <20240529080358.703784-1-xu.yang_2@nxp.com>
References: <20240529080358.703784-1-xu.yang_2@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?RfsEQLoBqNSKhUNCRGEEQb7JZdtEds95M/R7xIMhzlOtcF7lwE9bKKrTk6YH?=
 =?us-ascii?Q?flnf81xLw05VmFWF3zlpQLJFpyuPlvYbd5nZLIp7pc2DqBcPQdqhSvo8EhMy?=
 =?us-ascii?Q?sx/yrip3QiyP+OKdWpwG8art3DX4+vJVx+ozEjLWP3PMQCSG8PnhapTMHbtM?=
 =?us-ascii?Q?JnAEkzylVjPsN2eSnWF8njmSDFQhOURaQYubXQ7/GLv8a09kLgw1dsPQcygU?=
 =?us-ascii?Q?mYz62wkeEFITdeBXkPRf75xYWXx/UOIHttRAid+box8LT+Gp8gcqXiH5VI51?=
 =?us-ascii?Q?jeMpttWMulTgaGHsDeOp1vRTRs49iFKSL3MVGB2kWfWG+taz15WlLlGlLddC?=
 =?us-ascii?Q?DNsi/EAwEdNUO9vesRGjUVAmCuFlrH7kh3k5zpnvs9le5OtRczpzAnRHcVP4?=
 =?us-ascii?Q?yk0xMhxEiZ5KKEmLz7ZJH0duMR++BMnuF6/vMxd/blh0EJZVO2k2JS1M32gV?=
 =?us-ascii?Q?lkdUs+olDz66RxUQuVHItr5U83WWFyrnw9V4LElN4Hnsj7351KydiXAwmXTG?=
 =?us-ascii?Q?YJuonnkfohgAVfl5hd8XE5T5I6vCtOo4vdo2G2I11Xcc4BixwgSPaYQTTEDz?=
 =?us-ascii?Q?OCO6wd5yu13bCe5M8IpzTDDlKOwKcbR7bZeg7WWoGHyNgCOsXIgaor5rmkvb?=
 =?us-ascii?Q?clwq1atlLbPcpgZl87kd4mUh6fLNgc3c+SfyCPQFUv7f9XoAiGJh50LpRuM2?=
 =?us-ascii?Q?MJNbY6RigaYhyD1X79Gq3kaqKvb3td02oP1hLqRDp1HMgDG42kLG42GEmIV7?=
 =?us-ascii?Q?p90PrWGCYUqgHz5OseWljC6aebwl5HPdxNqS4nMeg5DmDfVyb/2IFSHVRJq8?=
 =?us-ascii?Q?e3pte/tQRJL/yp9Yo9JSM+D4dcDVfTTKS/haLnWWHkbD5uZ9CtNxtFROS1oD?=
 =?us-ascii?Q?A+bS31gVKhb/tEkXHcqd7X3Wte0I9MdS8LM4y3PRKBHOuW5sb6iZiZTsObMz?=
 =?us-ascii?Q?uzPd6tlfoe8jIWzXI34MDyB7Ic2f5xVHH74fEhQmstQAaKT+9lZrWqVgxxID?=
 =?us-ascii?Q?Y/t+e98gw3u0k6qR6G3g7AOe8PSp+WdeKKVIfFqR7NIsOtILWAXCSpFkvNry?=
 =?us-ascii?Q?zH3ECmwrkRWpEn/adwFXkZQwn0drjhY9nYAtv5m0JNs16sEHJ1lZtDUFTKDV?=
 =?us-ascii?Q?0SwIMOFpZPjKQst+vOg3dPbqviNlka4WeUDqpJkXyF5XZk4bEZEQkTATxKGm?=
 =?us-ascii?Q?Ou5gJYfHZ3+5UJQYb3kov/0SfTtvGgIIfpxcLSBqkuSqKexEqb/WCQON8OGh?=
 =?us-ascii?Q?hGL7AXLoApyxxehZELldUCJ+eBExiVPtucJ+p+eazTdMQn0nYyi6qwjUkIMV?=
 =?us-ascii?Q?NdpcLcdGflnKcYduzUk0ZUdwr61L2ANQSHIl8VtY7RGl4wb60vb0YagQrJla?=
 =?us-ascii?Q?QT6FYTjZmSnsjPu6efEKXqajkODhiH8YRnmTtBM5KWT1dYgXQRev5qhCkuqv?=
 =?us-ascii?Q?bYA4V3rogxHBlJkETg6iSOcnAnz1QviaHiDRUKkp5Lb98lwjFfKRx0Vx6dVS?=
 =?us-ascii?Q?zexhJmMWiWEr6x87a6LiTlsZC/bKwntbyodnee7Jvycbbkim4rX3HjvIwAWV?=
 =?us-ascii?Q?y34/SxWa8m49IWbs5h/TsVU3Yf1kxcS4uIlDQzH7?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 56a61e94-9ada-420f-fc99-08dc7fb60b74
X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8822.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2024 08:05:03.4249
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: JV0NXT4DtcmZTtjEsqLJqbxpPGdQYv6pU1pwG+S7X4EhClU4ThF06oThhG7Zw+7vD9C3rnSd4FjD9s34goO9Ng==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS1PR04MB9384

In current driver, the counter will start firstly and then be configured.
This sequence is not correct for AXI filter events since the correct
AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate.

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Fixes: 55691f99d417 ("drivers/perf: imx_ddr: Add support for NXP i.MX9 SoC DDRC PMU driver")
cc: <stable@vger.kernel.org>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>

---
Changes in v5:
 - new patch
Changes in v6:
 - no changes
Changes in v7:
 - no changes
Changes in v8:
 - add fix tag
Changes in v9:
 - add Rb tag
Changes in v10:
 - no changes
Changes in v11:
 - no changes
Changes in v12:
 - no changes
---
 drivers/perf/fsl_imx9_ddr_perf.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
index 5433c52a9872..7b43b54920da 100644
--- a/drivers/perf/fsl_imx9_ddr_perf.c
+++ b/drivers/perf/fsl_imx9_ddr_perf.c
@@ -541,12 +541,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
 	hwc->idx = counter;
 	hwc->state |= PERF_HES_STOPPED;
 
-	if (flags & PERF_EF_START)
-		ddr_perf_event_start(event, flags);
-
 	/* read trans, write trans, read beat */
 	imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2);
 
+	if (flags & PERF_EF_START)
+		ddr_perf_event_start(event, flags);
+
 	return 0;
 }
 
-- 
2.34.1