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AJvYcCVRLsYgRgQYQzwRAOF3ZMTTF9F4J2H0eF3QZU2LkX9kNXnpaxLlOEEvOusNFdR5KNeUS4+l3gBCBdxSxMzw8YrukYNIZDbx/MHPDHmX X-Gm-Message-State: AOJu0YzGJvJmsrGmqWPQw9/SjYPbPGNJH7jlrVwF8HQtIdfFpY2acywq wm7ur4c78mtUGjOTJp0uhlbClZyQRapQvc32oVwkw3ae6SFQGaBOZZyS+TMwdRdTqoLkNW0OEC8 DYaS4M1yyHsjlWlG7qhS6iFdECJ5AG/xSSK/JbQ== X-Received: by 2002:a4a:dcc4:0:b0:5b9:8dd6:3d62 with SMTP id 006d021491bc7-5b98dd649e1mr8998720eaf.0.1716975236516; Wed, 29 May 2024 02:33:56 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240524103307.2684-1-yongxuan.wang@sifive.com> <20240524103307.2684-3-yongxuan.wang@sifive.com> <20240527-widely-goatskin-bb5575541aed@spud> In-Reply-To: <20240527-widely-goatskin-bb5575541aed@spud> From: Yong-Xuan Wang Date: Wed, 29 May 2024 17:33:45 +0800 Message-ID: Subject: Re: [RFC PATCH v4 2/5] dt-bindings: riscv: Add Svadu Entry To: Conor Dooley Cc: linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, greentime.hu@sifive.com, vincent.chen@sifive.com, cleger@rivosinc.com, alex@ghiti.fr, Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Conor, On Mon, May 27, 2024 at 11:09=E2=80=AFPM Conor Dooley wr= ote: > > On Fri, May 24, 2024 at 06:33:02PM +0800, Yong-Xuan Wang wrote: > > Add an entry for the Svadu extension to the riscv,isa-extensions proper= ty. > > > > Signed-off-by: Yong-Xuan Wang > > Acked-by: Conor Dooley > > Reviewed-by: Andrew Jones > > I'm going to un-ack this, not because you did something wrong per se, > but because there's some discussion on the OpenSBI list about what is > and what is not backwards compatible and how an OS should interpret > svade and svadu: > https://lists.infradead.org/pipermail/opensbi/2024-May/006949.html > > Thanks, > Conor. > ok. I will remove it in the next version. Regards, Yong-Xuan > > --- > > Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/= Documentation/devicetree/bindings/riscv/extensions.yaml > > index 468c646247aa..598a5841920f 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -153,6 +153,12 @@ properties: > > ratified at commit 3f9ed34 ("Add ability to manually trigg= er > > workflow. (#2)") of riscv-time-compare. > > > > + - const: svadu > > + description: | > > + The standard Svadu supervisor-level extension for hardware= updating > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull= request > > + #25 from ved-rivos/ratified") of riscv-svadu. > > + > > - const: svinval > > description: > > The standard Svinval supervisor-level extension for fine-g= rained > > -- > > 2.17.1 > >