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Wed, 29 May 2024 11:47:50 +0200 Received: from lnxamnaw.se.axis.com (unknown [10.92.129.190]) by se-intmail01x.se.axis.com (Postfix) with ESMTP id 690F1AF6; Wed, 29 May 2024 11:47:50 +0200 (CEST) Received: by lnxamnaw.se.axis.com (Postfix, from userid 12778) id 5F2E32066B0; Wed, 29 May 2024 11:47:45 +0200 (CEST) From: Amna Waseem Date: Wed, 29 May 2024 11:47:44 +0200 Subject: [PATCH v2 1/2] dt-bindings: hwmon: ti,ina2xx: Add ti,alert-polarity property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20240529-apol-ina2xx-fix-v2-1-ee2d76142de2@axis.com> References: <20240529-apol-ina2xx-fix-v2-0-ee2d76142de2@axis.com> In-Reply-To: <20240529-apol-ina2xx-fix-v2-0-ee2d76142de2@axis.com> To: Jean Delvare , Guenter Roeck , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" CC: Krzysztof Kozlowski , , , , Amna Waseem , X-Mailer: b4 0.13.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM4PEPF00027A5D:EE_|AS2PR02MB10374:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e2725f1-ad43-49de-7abb-08dc7fc46814 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|376005|36860700004|82310400017|1800799015; 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X-OriginatorOrg: axis.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2024 09:47:51.5945 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e2725f1-ad43-49de-7abb-08dc7fc46814 X-MS-Exchange-CrossTenant-Id: 78703d3c-b907-432f-b066-88f7af9ca3af X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=78703d3c-b907-432f-b066-88f7af9ca3af;Ip=[195.60.68.100];Helo=[mail.axis.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A5D.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR02MB10374 Add a property to the binding to configure the Alert Polarity. Alert pin is asserted based on the value of Alert Polarity bit of Mask/Enable register. It is by default 0 which means Alert pin is configured to be active low open collector. Value of 1 maps to Inverted (active high open collector). Signed-off-by: Amna Waseem --- Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index df86c2c92037..5a16d2d94587 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -66,6 +66,14 @@ properties: description: phandle to the regulator that provides the VS supply typically in range from 2.7 V to 5.5 V. + ti,alert-polarity: + description: Alert polarity bit value of Mask/Enable register. Alert pin is + asserted based on the value of Alert polarity Bit. Default value is Normal + (0 which maps to active-low open collector). The other value is Inverted + (1 which maps to active-high open collector). + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + required: - compatible - reg @@ -88,5 +96,6 @@ examples: label = "vdd_3v0"; shunt-resistor = <1000>; vs-supply = <&vdd_3v0>; + ti,alert-polarity = <1>; }; }; -- 2.30.2