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Date: Wed, 29 May 2024 16:26:44 +0200
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Subject: Re: [PATCH v10 15/15] arm64: dts: qcom: sa8775p: add a dedicated
 memory carveout for TZ
To: Bartosz Golaszewski <brgl@bgdev.pl>,
 Bjorn Andersson <andersson@kernel.org>, Rob Herring <robh@kernel.org>,
 Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley
 <conor+dt@kernel.org>, Robert Marko <robimarko@gmail.com>,
 Das Srinagesh <quic_gurus@quicinc.com>,
 Bartosz Golaszewski <bartosz.golaszewski@linaro.org>,
 Maximilian Luz <luzmaximilian@gmail.com>,
 Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>,
 Srini Kandagatla <srinivas.kandagatla@linaro.org>,
 Arnd Bergmann <arnd@arndb.de>, Elliot Berman <quic_eberman@quicinc.com>,
 Alex Elder <elder@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
 kernel@quicinc.com
References: <20240527-shm-bridge-v10-0-ce7afaa58d3a@linaro.org>
 <20240527-shm-bridge-v10-15-ce7afaa58d3a@linaro.org>
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From: Konrad Dybcio <konrad.dybcio@linaro.org>
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In-Reply-To: <20240527-shm-bridge-v10-15-ce7afaa58d3a@linaro.org>
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On 27.05.2024 2:55 PM, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> 
> Add a 20MB reserved memory region for use by SCM calls.
> 
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/sa8775p.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 31de73594839..c183527452d7 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -208,6 +208,7 @@ core3 {
>  	firmware {
>  		scm {
>  			compatible = "qcom,scm-sa8775p", "qcom,scm";
> +			memory-region = <&tz_ffi_mem>;
>  		};
>  	};
>  
> @@ -418,6 +419,12 @@ cdt_data_backup_mem: cdt-data-backup@91ba0000 {
>  			no-map;
>  		};
>  
> +		tz_ffi_mem: tz-ffi@91c00000 {
> +			compatible = "shared-dma-pool";
> +			reg = <0x0 0x91c00000 0x0 0x1400000>;

How does that size relate to 

+	pool_config.max_size = SZ_256K;

in patch 3?

Konrad