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Date: Wed, 29 May 2024 11:00:49 -0400
From: Frank Li <Frank.li@nxp.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Richard Zhu <hongxing.zhu@nxp.com>,
	Lucas Stach <l.stach@pengutronix.de>,
	Lorenzo Pieralisi <lpieralisi@kernel.org>,
	Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
	Rob Herring <robh@kernel.org>, Bjorn Helgaas <bhelgaas@google.com>,
	Shawn Guo <shawnguo@kernel.org>,
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	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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	devicetree@vger.kernel.org, Jason Liu <jason.hui.liu@nxp.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v5 00/12] PCI: imx6: Fix\rename\clean up and add lut
 information for imx95
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References: <20240528-pci2_upstream-v5-0-750aa7edb8e2@nxp.com>
 <20240528223136.GA473846@bhelgaas>
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On Tue, May 28, 2024 at 05:31:36PM -0500, Bjorn Helgaas wrote:
> On Tue, May 28, 2024 at 03:39:13PM -0400, Frank Li wrote:
> > Fixed 8mp EP mode problem.
> > 
> > imx6 actaully for all imx chips (imx6*, imx7*, imx8*, imx9*). To avoid     
> > confuse, rename all imx6_* to imx_*, IMX6_* to IMX_*. pci-imx6.c to        
> > pci-imx.c to avoid confuse.                                                
> > 
> > Using callback to reduce switch case for core reset and refclk.            
> > 
> > Add imx95 iommux and its stream id information.                            
> > 
> > Base on linux-pci/controller/imx
> 
> This applies cleanly to the pci/controller/gpio branch, which has some
> minor rework in pci-imx6.c.
> 
> When we apply this, I think we should do it on a a pci/controller/imx6
> branch that is based on "main" (v6.10-rc1).
> 
> I can resolve the conflicts with pci/controller/gpio when building
> pci/next.

Sorry, I forget update this. It should be base on linux-pci/next
(e3fca37312892122d73f8c5293c0d1cc8c34500b). 

commit e3fca37312892122d73f8c5293c0d1cc8c34500b (pci/next, linux-pci/next)
Merge: 86e0cd3da71b5 d19a86d584e04
Author: Bjorn Helgaas <bhelgaas@google.com>
Date:   Tue May 28 12:34:12 2024 -0500

    Merge branch 'pci/controller/tegra194'
    
    - Ensure Tegra194 and Tegra234 inbound ATU entries are 64KB-aligned to
      match the hardware restriction (Jon Hunter)
    
    * pci/controller/tegra194:
      PCI: tegra194: Set EP alignment restriction for inbound ATU


> 
> Bjorn