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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: analog.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR03MB4320.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c8f38b10-4293-4ba3-43df-08dc7ff02abd X-MS-Exchange-CrossTenant-originalarrivaltime: 29 May 2024 15:01:06.5176 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: eaa689b4-8f87-40e0-9c6f-7228de4d754a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: pA1eQwo0jno8HbPd8ZkpZknhQO72t/mpr2ywYeLtOQvlzQYUeJjvhqKjOjxu8tTV8NKrCbeRkMq61X4AJzx4YyUMfQwzakczntRx2Q77OV4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR03MB7086 X-Proofpoint-GUID: 2OwRLKIVvF017WC59Bnsj78Dj_JpLaSE X-Proofpoint-ORIG-GUID: 2OwRLKIVvF017WC59Bnsj78Dj_JpLaSE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-29_11,2024-05-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 adultscore=0 spamscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2405290103 Hello,=20 Thank you for the review. I implemented most of your comments, excepting so= me things that were slightly unclear to me or I had a different explanation= I left a couple of comments below, and I will send a new patch in a separ= ate email. >On Wed, May 22, 2024 at 02:59:53PM +0300, ranechita wrote: >> Added support for ad7770,ad7771,ad7779 ADCs. The data is streamed only=20 >> on the spi-mode, without using the data lines. > >> --- > >Please, explain here, in the comment area, why any existing driver can not= be reused (extended) for these ADCs. > >... > >> +#include > >This header must not be in the new code. > >... > >> +#define AD777X_SINC3_MAXFREQ 16000 >> +#define AD777X_SINC5_MAXFREQ 128000 > >HZ_PER_KHZ ? You will need units.h. > >... > >> +#define DEC3 1000 >> +#define DEC6 1000000 > >NIH some of units.h constants. Use them. > >... > > >> + /* >> + * DMA (thus cache coherency maintenance) requires the >> + * transfer buffers to live in their own cache lines. >> + */ >> + u8 reg_rx_buf[3] ____cacheline_aligned; >> + u8 reg_tx_buf[3]; > >> + u8 spidata_rx[32]; >> + u8 spidata_tx[32]; > >These will not be cache aligned. Is it a problem? No, it should be fine without the alignment. > ------ > >> +{ >> + int ret; >> + u8 regval, data; >> + >> + ret =3D ad777x_spi_read(st, reg, &data); >> + if (ret) >> + return ret; >> + >> + regval =3D data; >> + regval &=3D ~mask; >> + regval |=3D val; >> + >> + if (regval !=3D data) { >> + ret =3D ad777x_spi_write(st, reg, regval); >> + if (ret) >> + return ret; >> + } >> + >> + return 0; > >This all can be written as > > if (regval !=3D data) > return ad777x_spi_write(st, reg, regval); > > return 0; > >...or... > > if (regval =3D=3D data) > return 0; > > return ad777x_spi_write(st, reg, regval); > >(I prefer the latter as it shows better the flow) > >> +} > >No mutex no nothing for RMW op like this? > >Btw, can't you use regmap for IO? Unfortunately, I don't think regmap could be used, because of the crc and t= he fact that data is shifted out on the SPI SDO line in the interrupt. I co= nsider perhaps adding regmap to the mix might complicate things a bit.=20 > >... > >> + if (st->filter_enabled =3D=3D AD777X_SINC3 && >> + sampling_freq > AD777X_SINC3_MAXFREQ) { >> + return -EINVAL; >> + } else if (st->filter_enabled =3D=3D AD777X_SINC5 && > >Redundant 'else' > >> + sampling_freq > AD777X_SINC5_MAXFREQ) { > >Broken indentation. > >> + return -EINVAL; >> + } > >Unneeded {}. > >... > >> + ret =3D ad777x_spi_write(st, AD777X_REG_SRC_N_LSB, lsb); >> + if (ret) >> + return ret; >> + ret =3D ad777x_spi_write(st, AD777X_REG_SRC_N_MSB, msb); >> + if (ret) >> + return ret; > >Can you use 16-bit writes? >Same Q to all similar LSB/MSB write groups. I cannot do 16-bit writes due to how the spi functions on the chip and beca= use the registers for MSB/LSB are at different addresses. >-------- >> +static void ad777x_clk_disable(void *data) { >> + clk_disable_unprepare(data); >> +} > >See below. > >... > >> + st->mclk =3D devm_clk_get(&spi->dev, "mclk"); >> + if (IS_ERR(st->mclk)) >> + return PTR_ERR(st->mclk); >> + >> + ret =3D clk_prepare_enable(st->mclk); >> + if (ret < 0) >> + return ret; > >> + ret =3D devm_add_action_or_reset(&spi->dev, >> + ad777x_clk_disable, >> + st->mclk); >> + if (ret) >> + return ret; > >So, what's wrong with the _enabled() API? Sorry, I am not sure what you mean here by _enabled() API, is there a diffe= rent mechanism that can be used for this type of operations? Best Regards, Ramona=20