Received-SPF: pass (google.com: domain of linux-kernel+bounces-194747-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Message-ID: <ed3236173ff6fdb1cb6962f388b41e6b90586335.camel@linux.intel.com>
Subject: Re: [PATCH 1/2] HID: intel-ish-hid: fix cache management mistake
From: srinivas pandruvada <srinivas.pandruvada@linux.intel.com>
To: Arnd Bergmann <arnd@arndb.de>, Lixu Zhang <lixu.zhang@intel.com>, Arnd
 Bergmann <arnd@kernel.org>, Jiri Kosina <jikos@kernel.org>, Benjamin
 Tissoires <bentiss@kernel.org>
Cc: "linux-input@vger.kernel.org" <linux-input@vger.kernel.org>, 
	"linux-kernel@vger.kernel.org"
	 <linux-kernel@vger.kernel.org>
Date: Wed, 29 May 2024 15:25:22 -0700
In-Reply-To: <fcbdc4a5-abee-4de8-9fe8-c8486195b96d@app.fastmail.com>
References: <20240528115802.3122955-1-arnd@kernel.org>
	 <DM4PR11MB5995875EEC9ACCFC43D8B86A93F22@DM4PR11MB5995.namprd11.prod.outlook.com>
	 <fcbdc4a5-abee-4de8-9fe8-c8486195b96d@app.fastmail.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
User-Agent: Evolution 3.50.0-1 
Precedence: bulk
MIME-Version: 1.0

On Wed, 2024-05-29 at 09:06 +0200, Arnd Bergmann wrote:
> On Wed, May 29, 2024, at 08:46, Zhang, Lixu wrote:
> > >=20
> > > -#include <linux/cacheflush.h>
> > > #include <linux/container_of.h>
> > > #include <linux/dev_printk.h>
> > > #include <linux/dma-mapping.h>
> > > @@ -175,10 +174,11 @@ static int prepare_dma_bufs(struct
> > > ishtp_device
> > > *dev,
> > > 			return -ENOMEM;
> > >=20
> > > 		fragment->fragment_tbl[i].ddr_adrs =3D
> > > cpu_to_le64(dma_addr);
> > > +
> > > +		memcpy(dma_bufs[i], ish_fw->data + offset,
> > > fragment-
> > > > fragment_tbl[i].length);
> > fragment->fragment_tbl[i].length was used before assignment.
> >=20
> > > +		dma_wmb();
> > I tested it on the platform, but it didn't wok.
> >=20
>=20
> What behavior do you see instead? If the manual cache
> flush works around a bug, that would indicate that the
> device itself is not coherent and the dma_alloc_coherent()
> in the architecture is broken.

Lixu,

What happens if you remove manual cache flush in your code?
It is possible that boot loader at this time not ready to do fully
coherent ops.

Thanks,
Srinivas


>=20
> =C2=A0=C2=A0=C2=A0=C2=A0 Arnd